参数资料
型号: XC4013XL-3BG256I
厂商: XILINX INC
元件分类: FPGA
英文描述: XC4000E and XC4000X Series Field Programmable Gate Arrays
中文描述: FPGA, 576 CLBS, 10000 GATES, 166 MHz, PBGA256
文件页数: 10/16页
文件大小: 69K
代理商: XC4013XL-3BG256I
R
DS005 (v. 1.8 October 18, 1999 - Product Specication
6-75
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000XL A.C. Characteristics
Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB ip-ops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature. Values apply to all XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
Global Low Skew Buffer to Clock K
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Delay from pad through GLS buffer to
any clock input, K
TGLS
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
0.3
0.4
0.5
0.6
0.7
0.9
1.1
1.2
1.3
1.4
1.6
2.1
2.7
3.2
3.6
4.0
4.4
4.8
5.3
5.7
6.3
7.2
1.8
2.3
2.8
3.1
3.5
3.8
4.2
4.6
5.0
5.4
6.2
1.6
2.0
2.4
2.7
3.0
3.3
3.6
4.0
4.5
4.7
5.7
1.5
1.9
2.3
2.6
2.9
3.2
3.5
3.9
4.4
4.6
5.5
2.3
3.1
4.0
ns
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