参数资料
型号: XC4VLX100-10FFG1148C
厂商: Xilinx Inc
文件页数: 35/58页
文件大小: 0K
描述: IC FPGA VIRTEX-4 100K 1148-FBGA
标准包装: 1
系列: Virtex®-4 LX
LAB/CLB数: 12288
逻辑元件/单元数: 110592
RAM 位总计: 4423680
输入/输出数: 768
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 1148-BBGA,FCBGA
供应商设备封装: 1148-FCPBGA(35x35)
其它名称: 122-1486
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
40
Table 47: Input Clock Tolerances
Symbol
Description
Frequency
Range
Value
Units
Duty Cycle Input Tolerance (in %)
CLKIN_PSCLK_PULSE_RANGE_1
PSCLK only
< 1 MHz
25 - 75
%
CLKIN_PSCLK_PULSE_RANGE_1_50
PSCLK and CLKIN
1 – 50 MHz(1)
25 - 75
%
CLKIN_PSCLK_PULSE_RANGE_50_100
50 – 100 MHz(1)
30 - 70
%
CLKIN_PSCLK_PULSE_RANGE_100_200
100 – 200 MHz(1)
40 - 60
%
CLKIN_PSCLK_PULSE_RANGE_200_400
200 – 400 MHz(1)
45 - 55
%
CLKIN_PSCLK_PULSE_RANGE_400
> 400 MHz
45 - 55
%
Speed Grade
-12
-11
-10
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN_CYC_JITT_DLL_LF
CLKIN (using DLL outputs)(2,5,6)
±300
±345
ps
CLKIN_CYC_JITT_FX_LF
CLKIN (using DFS outputs)(3)
±300
±345
ps
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN_CYC_JITT_DLL_HF
CLKIN (using DLL outputs)(2,5,6)
±150
±173
ps
CLKIN_CYC_JITT_FX_HF
CLKIN (using DFS outputs)(3)
±150
±173
ps
Input Clock Period Jitter (Low Frequency Mode)
CLKIN_PER_JITT_DLL_LF
CLKIN (using DLL outputs)(2,5,6)
±1.0
±1.15
ns
CLKIN_PER_JITT_FX_LF
CLKIN (using DFS outputs)(3)
±1.0
±1.15
ns
Input Clock Period Jitter (High Frequency Mode)
CLKIN_PER_JITT_DLL_HF
CLKIN (using DLL outputs)(2,5,6)
±1.0
±1.15
ns
CLKIN_PER_JITT_FX_HF
CLKIN (using DFS outputs)(3)
±1.0
±1.15
ns
Feedback Clock Path Delay Variation
CLKFB_DELAY_VAR_EXT
CLKFB off-chip feedback
±1.0
±1.15
ns
Notes:
1.
For boundary frequencies, use the more restrictive specifications.
2.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
3.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
4.
If both DLL and DFS outputs are used, follow the more restrictive specifications.
5.
The DCM must be reset if the clock input clock stops for more than 100 ms.
6.
These values also apply when using both DLL and DFS outputs.
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