参数资料
| 型号： | XC5202-6PC84C |
| 厂商： | Xilinx Inc |
| 文件页数： | 24/73页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 64 CLB'S 84-PLCC |
| 产品变化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 标准包装： | 15 |
| 系列： | XC5200 |
| LAB/CLB数： | 64 |
| 逻辑元件/单元数： | 256 |
| 输入/输出数： | 65 |
| 门数： | 3000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 84-LCC（J 形引线） |
| 供应商设备封装： | 84-PLCC |
| 其它名称： | 122-1131 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页
R
XC5200 Series Field Programmable Gate Arrays
7-112
November 5, 1998 (Version 5.2)
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
Release of Global Reset After DONE Goes High
By default, Global Reset (GR) is released two CCLK cycles
after the DONE pin goes High. If CCLK is not clocked twice
after DONE goes High, all flip-flops are held in their initial
reset state. The delay from DONE High to GR inactive is
controlled by an option to the bitstream generation soft-
ware.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 25 on page 109. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
Configuration Through the Boundary Scan
Pins
XC5200-Series devices can be configured through the
boundary scan pins.
For detailed information, refer to the Xilinx application note
XAPP017, “
Boundary Scan in XC4000 and XC5200
Devices.”
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs.
DONE
*
**
QS
R
1
0
1
0
1
0
1
0
1
GR ENABLE
GR INVERT
STARTUP.GR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
GLOBAL RESET OF
ALL CLB FLIP-FLOPS/LATCHES
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
Q2
Q3
Q1/Q4
DONE
IN
STARTUP
Q0
Q1
Q2
Q3
Q4
M
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
K
SQ
K
DQ
K
DQ
K
DQ
K
DQ
FULL
LENGTH COUNT
CLEAR MEMORY
CCLK
STARTUP.CLK
USER NET
CONFIGURATION BIT OPTIONS SELECTED BY USER
X9002
Figure 26: Start-up Logic
Product Obsolete or Under Obsolescence
相关PDF资料 |
PDF描述 |
|---|---|
| FMC31DRXH | CONN EDGECARD 62POS DIP .100 SLD |
| XC4036XL-2HQ240C | IC FPGA 1296 CLB'S 240-HQFP |
| ABB60DHAS-S793 | CONN EDGECARD 120POS R/A .05 REV |
| IDT71V424S12YG | IC SRAM 4MBIT 12NS 36SOJ |
| FMM24DSEI-S13 | CONN EDGECARD 48POS .156 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC5202-6PC84I | 制造商:Xilinx 功能描述: |
| XC5202-6PG156C | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-6PG191C | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-6PG223C | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays |
| XC5202-6PG299C | 制造商:XILINX 制造商全称:XILINX 功能描述:Field Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。