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参数资料
| 型号： | XC68307FG8V |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 3/35页 |
| 文件大小： | 172K |
| 代理商： | XC68307FG8V |
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MOTOROLA
MC68307 TECHNICAL INFORMATION
11
Low-Power Stop Logic
Various options for power-saving are available: turning off unused peripherals, reducing processor clock speed,
disabling the processor altogether or a combination of these.
A wake-up from power-down can be achieved by causing an interrupt at the interrupt controller logic which runs
throughout the period of processor power-down. Any interrupt will cause a wake-up of the EC000 core followed
by processing of that interrupt.
The on-chip peripherals can initiate a wake-up; for example, the timer can be set to wake-up after a certain
elapsed time, or number of external events, or the UART can cause a wake-up on receiving serial data.
The clocks provided to the various internal modules can all be disabled to further reduce power consumption. In
the case of the UART, its clock is restarted automatically by a transition on the RxD pin, so that incoming data is
clocked in. When the data has been completely received, an interrupt from the UART wakes-up the processor
core. If the other on-chip peripherals (the timer and M-bus) are required to cause a wake-up, then their clocks
should not be disabled in this manner.
JTAG Test Access Port
To aid in system diagnostics the MC68307 includes dedicated user-accessible test logic that is fully compliant
with the IEEE 1149.1 standard for boundary scan testability, often referred to as JTAG (joint test action group).
SIM07 Programming Model
The SIM07 programming model is listed in Tables 3–7. The FC (function code) column in each table indicates
whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user
space (S/U). With the exception of the system configuration registers (listed in Table 3), the address column
of each table contains the offset from the base address (MBASE) contained in the MBAR.
Table 3. SIM07 System Conguration Registers
Address
FC
Register Name
$0000F0
—
Reserved—No external bus access
$0000F2
S
Module Base Address Register (MBAR)
$0000F4
S
System Control Register (SCR)
$0000F6
S
System Control Register (SCR)
$0000F8
—
Reserved—No external bus access
$0000FA
—
Reserved—No external bus access
$0000FC
—
Reserved—No external bus access
$0000FE
—
Reserved—No external bus access
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