参数资料
型号: XC6SLX150T-2FG484I
厂商: Xilinx Inc
文件页数: 8/89页
文件大小: 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
标准包装: 60
系列: Spartan® 6 LXT
LAB/CLB数: 11519
逻辑元件/单元数: 147443
RAM 位总计: 4939776
输入/输出数: 296
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BBGA
供应商设备封装: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
16
Table 21: GTP Transceiver User Clock Switching Characteristics(1)
Symbol
Description
Conditions
Speed Grade
Units
-3
-3N
-2
-1L
FTXOUT
TXOUTCLK maximum frequency
320
270
N/A
MHz
FRXREC
RXRECCLK maximum frequency
320
270
N/A
MHz
TRX
RXUSRCLK maximum frequency
320
270
N/A
MHz
TRX2
RXUSRCLK2 maximum frequency
1 byte interface
156.25
125
N/A
MHz
2 byte interface
160
125
N/A
MHz
4 byte interface
80
67.5
N/A
MHz
TTX
TXUSRCLK maximum frequency
320
270
N/A
MHz
TTX2
TXUSRCLK2 maximum frequency
1 byte interface
156.25
125
N/A
MHz
2 byte interface
160
125
N/A
MHz
4 byte interface
80
67.5
N/A
MHz
Notes:
1.
Clocking must be implemented as described in UG386: Spartan-6 FPGA GTP Transceivers User Guide.
Table 22: GTP Transceiver Transmitter Switching Characteristics
Symbol
Description
Condition
Min
Typ
Max
Units
TRTX
TX Rise time
20%–80%
140
ps
TFTX
TX Fall time
80%–20%
120
ps
TLLSKEW
TX lane-to-lane skew(1)
400
ps
VTXOOBVDPP
Electrical idle amplitude
20
mV
TTXOOBTRANSITION
Electrical idle transition time
50
ns
TJ3.125
Total Jitter(2)
3.125 Gb/s
0.35
UI
DJ3.125
Deterministic Jitter(2)
0.15
UI
TJ2.5
Total Jitter(2)
2.5 Gb/s
0.33
UI
DJ2.5
Deterministic Jitter(2)
0.15
UI
TJ1.62
Total Jitter(2)
1.62 Gb/s
0.20
UI
DJ1.62
Deterministic Jitter(2)
0.10
UI
TJ1.25
Total Jitter(2)
1.25 Gb/s
0.20
UI
DJ1.25
Deterministic Jitter(2)
0.10
UI
TJ614
Total Jitter(2)
614 Mb/s
0.10
UI
DJ614
Deterministic Jitter(2)
0.05
UI
Notes:
1.
Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.
2.
Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
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