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参数资料
| 型号： | XC7455ARX1000LF |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 45/76页 |
| 文件大小： | 1520K |
| 代理商： | XC7455ARX1000LF |
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MOTOROLA
MPC7455 RISC Microprocessor Hardware Specifications
5
Features
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set-associative instruction and data caches
— Pseudo least-recently-used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software
— Caches can be locked in software
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— Parity support on cache and tags
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 256-Kbyte, eight-way set-associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
— PLRU replacement algorithm
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— 64-byte, two-sectored line size
— Parity support on cache
Level 3 (L3) cache interface (not implemented on MPC7445)
— Provides critical double-word forwarding to the requesting unit
— Internal L3 cache controller and tags
— External data SRAMs
— Support for 1- and 2-Mbyte L3 caches
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相关代理商/技术参数 |
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| XC74UH | 制造商:TOREX 制造商全称:Torex Semiconductor 功能描述:XC74UH |
| XC74UH00AAM | 制造商:TOREX 制造商全称:Torex Semiconductor 功能描述:XC74UH |
| XC74UH02AAM | 制造商:TOREX 制造商全称:Torex Semiconductor 功能描述:XC74UH |
| XC74UH04AAM | 制造商:TOREX 制造商全称:Torex Semiconductor 功能描述:XC74UH |
| XC74UH08AAM | 制造商:TOREX 制造商全称:Torex Semiconductor 功能描述:XC74UH |
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