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参数资料
| 型号： | XC7455ARX1000LF |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, CBGA483 |
| 封装： | 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483 |
| 文件页数： | 8/76页 |
| 文件大小： | 1520K |
| 代理商： | XC7455ARX1000LF |
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16
MPC7455 RISC Microprocessor Hardware Specifications
MOTOROLA
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
1.5.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC7455 as defined in Figure 4 and
Figure 5. Timing specifications for the L3 bus are provided in Section 1.5.2.3, “L3 Clock AC
Specifications.”
Internal PLL relock time
—100
s5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL
Configuration,” for valid PLL_CFG[0:4] settings.
2. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
3. Timing is guaranteed by design and characterization.
4. This represents total input jitter—short term and long term combined—and is guaranteed by design.
5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also
note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the
power-on reset sequence.
6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See Table 4.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
733 MHz
867 MHz
933 MHz
1 GHz
Min
Max
Min
Max
Min
Max
Min
Max
SYSCLK
VM
CVIH
CVIL
VM = Midpoint Voltage (OVDD/2)
tSYSCLK
tKR
tKF
tKHKL
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