参数资料
| 型号： | XCS20-3PQ208I |
| 厂商： | Xilinx Inc |
| 文件页数： | 67/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V I-TEMP 208-PQFP |
| 产品变化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 标准包装： | 24 |
| 系列： | Spartan® |
| LAB/CLB数： | 400 |
| 逻辑元件/单元数： | 950 |
| RAM 位总计： | 12800 |
| 输入/输出数： | 160 |
| 门数： | 20000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
The register choice is made by placing the appropriate
library symbol. For example, IFD is the basic input flip-flop
(rising edge triggered), and ILD is the basic input latch
(transparent-High). Variations with inverted clocks are also
available. The clock signal inverter is also shown in Figure 5
on the CK line.
The Spartan family IOB data input path has a one-tap delay
element: either the delay is inserted (default), or it is not.
The Spartan-XL family IOB data input path has a two-tap
delay element, with choices of a full delay, a partial delay, or
no delay. The added delay guarantees a zero hold time with
respect to clocks routed through the global clock buffers.
(See Global Nets and Buffers, page 12 for a description of
the global clock buffers in the Spartan/XL families.) For a
shorter input register setup time, with positive hold-time,
attach a NODELAY attribute or property to the flip-flop.The
output of the input register goes to the routing channels (via
I1 and I2 in Figure 6). The I1 and I2 signals that exit the IOB
can each carry either the direct or registered input signal.
The 5V Spartan family input buffers can be globally config-
ured for either TTL (1.2V) or CMOS (VCC/2) thresholds,
using an option in the bitstream generation software. The
Spartan family output levels are also configurable; the two
global adjustments of input threshold and output level are
independent. The inputs of Spartan devices can be driven
by the outputs of any 3.3V device, if the Spartan family
inputs are in TTL mode. Input and output thresholds are
TTL on all configuration pins until the configuration has
been loaded into the device and specifies how they are to
be used. Spartan-XL family inputs are TTL compatible and
3.3V CMOS compatible.
Supported sources for Spartan/XL device inputs are shown
in Table 4.
Spartan-XL family I/Os are fully 5V tolerant even though the
VCC is 3.3V. This allows 5V signals to directly connect to the
Spartan-XL family inputs without damage, as shown in
after 5V signals are applied to the I/Os. This makes the
Spartan-XL devices immune to power supply sequencing
problems.
Figure 6: Simplified Spartan/XL IOB Block Diagram
Multiplexer Controlled
by Configuration Program
T
O
OK
Q
GTS
D
CK
EC
I1
I2
IK
EC
Q
D
CK
EC
Delay
Package
Pad
Programmable
Pull-Up/
Pull-Down
Network
OUTPUT DRIVER
Programmable Slew Rate
Programmable TTL/CMOS Drive
(Spartan only)
INPUT BUFFER
DS060_06_041901
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS20-3PQ240C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-3PQ240I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS20-3PQ256C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-3PQ256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-3PQ280C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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