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| 型号： | XCS20-3TQ84I |
| 厂商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴达和Spartan - xL的家庭现场可编程门阵列 |
| 文件页数： | 32/82页 |
| 文件大小： | 863K |
| 代理商： | XCS20-3TQ84I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
38
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfering
with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Although readback can be performed while the device is
operating, for best results and to freeze a known capture
state, it is recommended that the clock inputs be stopped
until readback is complete.
Readback of Spartan-XL Express mode bitstreams results
in data that does not resemble the original bitstream,
because the bitstream format differs from other modes.
Spartan/XL Readback does not use any dedicated pins, but
uses
four
internal
nets
(RDBK.TRIG,
RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, instantiate the
READBACK library symbol and attach the appropriate pad
symbols, as shown in Figure 32.
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress) out-
put goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit (Low)
of the first frame. The first two data bits of the first frame are
always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the bitstream
generation software.
Readback Capture
When the Readback Capture option is selected, the data
stream includes sampled values of CLB and IOB signals.
The rising edge of RDBK.TRIG latches the inverted values
of the four CLB outputs, the IOB output flip-flops and the
input signals I1 and I2. Note that while the bits describing
configuration (interconnect, function generators, and RAM
content) are not inverted, the CLB and IOB output signals
are inverted. RDBK.TRIG is located in the lower-left corner
of the device.
When the Readback Capture option is not selected, the val-
ues of the capture bits reflect the configuration data origi-
nally written to those memory locations. If the RAM
capability of the CLBs is used, RAM data are available in
Readback, since they directly overwrite the F and G func-
tion-table configuration of the CLB.
Figure 32: Readback Schematic Example
READBACK
DATA
RIP
TRIG
CLK
READ_DATA
OBUF
READ_TRIGGER
IBUF
DS060_31_080400
If Unconnected,
Default is CCLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS20-3TQG144I | 制造商:Xilinx 功能描述:IC LOGIC CELLS |
| XCS20-3VQ100C | 功能描述:IC FPGA 5V C-TEMP 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan® 标准包装:1 系列:Kintex-7 LAB/CLB数:25475 逻辑元件/单元数:326080 RAM 位总计:16404480 输入/输出数:350 门数:- 电源电压:0.97 V ~ 1.03 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:900-BBGA，FCBGA 供应商设备封装:900-FCBGA（31x31） 其它名称:122-1789 |
| XCS20-3VQ100I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-3VQ144C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-3VQ144I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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