- 您现在的位置：买卖IC网 > PDF目录4056 > XPC8240LVV200E (Freescale Semiconductor)IC MPU INTEGRATED 200MHZ 352TBGA PDF资料下载
参数资料
| 型号： | XPC8240LVV200E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/52页 |
| 文件大小： | 0K |
| 描述： | IC MPU INTEGRATED 200MHZ 352TBGA |
| 标准包装： | 24 |
| 系列： | MPC82xx |
| 处理器类型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 电压： | 2.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 352-LBGA |
| 供应商设备封装： | 352-TBGA（35x35） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
MPC8240 Integrated Processor Hardware Specifications
37
System Design Information
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then
returned to the SDRAM_SYNC_IN input of the MPC8240. The trace length may be used to skew or adjust
the timing window as needed. See the Motorola application note AN1794, “Backside L2 Timing Analysis
for PCB Design Engineers,” for more information on this topic.
1.7.5
Pull-Up/Pull-Down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress; therefore, they
do not require pull-up resistors on the bus. The data bus signals are: DH[0:31], DL[0:31], and PAR[0:7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (DL[0:31] and
PAR[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be
driven. For this mode, these pins do not require pull-up resistors and should be left unconnected by the
system to minimize possible output switching.
The TEST0 pins require pull-up resistors of 120
or less connected to OV
DD.
It is recommended that TEST2 have a weak pull-up resistor (2–10 k
) connected to GV
DD.
It is recommended that the following signals be pulled up to OVDD with weak pull-up resistors (2–10 k
):
SDA, SCL, SMI, SRESET, TBEN, CHKSTOP_IN, and TEST1.
It is recommended that the following PCI control signals be pulled up to LVDD with weak pull-up resistors
(2–10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, TRDY, and INTA. The resistor values
may need to be adjusted stronger to reduce induced noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0:3], REQ4/DA4, TCK, TDI,
TMS, and TRST. See Table 17 for more information.
The following pins have internal pull-up resistors enabled only while the MPC8240 is in the reset state:
GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0:2], PMAA[0:2], and
QACK/DA0. See Table 17 for more information.
The following pins are reset configuration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS, MCP,
QACK/DA0, MAA[0:2], PMAA[0:2], and PLL_CFG[0:4]/DA[10:6]. These pins are sampled during reset
to configure the device.
Reset configuration pins should be tied to GND via 1-k
pull-down resistors to ensure a logic 0 level is read
into the configuration bits during reset if the default logic 1 level is not desired.
Any other unused active-low input pins should be tied to a logic one level through weak pull-up resistors
(2–10 k
) to the appropriate power supply. Unused active-high input pins should be tied to GND through
weak pull-down resistors (2–10 k
).
1.7.6
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. While
it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable
power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because
the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8360CZUAJDGA | IC MPU POWERQUICC II PRO 740TBGA |
| MPC8360CVVAJDGA | IC MPU POWERQUICC II PRO 740TBGA |
| MPC862TCZQ50B | IC MPU PWRQUICC 80MHZ 357-PBGA |
| MPC862TCVR50B | IC MPU POWERQUICC 50MHZ 357PBGA |
| XCS20-4TQ144C | IC FPGA 5V C-TEMP 144-TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XPC8240LZU200C | 制造商:Freescale Semiconductor 功能描述: |
| XPC8240LZU200E | 功能描述:微处理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| XPC8240RVV250 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Modified voltage specifications to achieve 250 MHz |
| XPC8240RVV250E | 功能描述:微处理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| XPC8240RZU250 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Modified voltage specifications to achieve 250 MHz |
发布紧急采购，3分钟左右您将得到回复。