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参数资料
| 型号： | XR16M554IL48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 4/46页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B QUAD 48QFN |
| 标准包装： | 260 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 16 字节 |
| 规程： | RS232 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN-EP（7x7） |
| 包装： | 托盘 |
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XR16M554/554D
12
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.0
2.4
Channels A-D Internal Registers
Each UART channel in the M554 has a set of enhanced registers for controlling, monitoring and data loading
and unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR). All the register functions are discussed in full detail later in “Section 3.0,
2.5
INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the M554 is placed in single-character mode for data transmit or
receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode
operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level.
TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or
FIFO empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16M554IV-0A-EVB | 功能描述:界面开发工具 Eval Board for XR16M554IV-0A RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M554IV-0B-EVB | 功能描述:界面开发工具 Eval Board for XR16M554IV-0B RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M554IV64 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO |
| XR16M554IV64-F | 功能描述:UART 接口集成电路 1.62V-3.63V QUAD UART W/ 16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16M554IV80 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO |
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