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参数资料
| 型号： | XR16M554IL48-F |
| 厂商： | Exar Corporation |
| 文件页数： | 7/46页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B QUAD 48QFN |
| 标准包装： | 260 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 16 字节 |
| 规程： | RS232 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN-EP（7x7） |
| 包装： | 托盘 |
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XR16M554/554D
15
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
2.9.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.9.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.9.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
Transmit Data Shift Register
( TSR)
Transmit
Data Byte
THR Interrupt (ISR bit-1)
When it becomes empty.
FIFO is Enabled by FCR
Bit-0=1
Transmit
FIFO
16X Clock
TXFIFO1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR16M554IV-0A-EVB | 功能描述:界面开发工具 Eval Board for XR16M554IV-0A RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M554IV-0B-EVB | 功能描述:界面开发工具 Eval Board for XR16M554IV-0B RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M554IV64 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO |
| XR16M554IV64-F | 功能描述:UART 接口集成电路 1.62V-3.63V QUAD UART W/ 16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16M554IV80 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO |
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