参数资料
| 型号： | XR16M670IL32-F |
| 厂商： | Exar Corporation |
| 文件页数： | 33/50页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 32B 32QFN |
| 标准包装： | 490 |
| 特点： | * |
| 通道数： | 1，UART |
| FIFO's： | 32 字节 |
| 规程： | RS232，RS422，RS485 |
| 电源电压： | 1.62 V ~ 3.63 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 托盘 |
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XR16M670
39
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-7, and DLD
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 3-5, MCR bits 5-
7, and DLD are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 3-5,
and MCR bits 5-7, and DLD are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the EFR[3:0] register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the selected trigger level and RTS de-
asserts HIGH at the next upper trigger level/hysteresis level. RTS# will return LOW when FIFO data falls below
the next lower trigger level/hysteresis level. The RTS# output must be asserted (LOW) before the auto RTS
can take effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.17
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Table 5. The xoff2 is also used as auto address detect register when the auto 9-bit mode
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| XR16M670IL32TR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 32Byte FIFO 1.8V/2.5V/3.3V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16M670IL32TR-F |
| XR16M680 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO |
| XR16M680IB25 | 制造商:EXAR 制造商全称:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO |
| XR16M680IB25-0C-EB | 功能描述:界面开发工具 Eval Board for XR16M680IB25 Series RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR16M680IB25-F | 功能描述:UART 接口集成电路 1.8 HIGH PERFORMANCE UART W/32 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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