参数资料
| 型号： | XR17D154IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 24/69页 |
| 文件大小： | 0K |
| 描述： | IC UART PCI BUS QUAD 144LQFP |
| 产品培训模块： | UART Product Overview |
| 标准包装： | 60 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS485 |
| 电源电压： | 3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
| 其它名称： | 1016-1290 |
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XR17D154
xr
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.2
30
5.3
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The
RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the
middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts
counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start
bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 1- 4 and an LSR interrupt is generated immediately if IER bit-2 is enabled.
Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach
the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1:0] plus 12 bits time.
The RHR interrupt is enabled by IER bit-0.
5.3.1
Receive Holding Register (RHR) - Read-Only
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by
11-bit wide, 4 extra bits are for the error tags to be in LSR register. When the FIFO is enabled by FCR bit-0, it
acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer
is bumped after the RHR register is read. Also, the error tags associated with the data byte are immediately
updated onto the line status register (LSR) bits 1-4.
5.3.2
Receiver Operation in non-FIFO Mode
FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE
R e c e iv e D a ta S h ift
Re g is te r ( R SR)
Re c e iv e
D a ta B y te
a n d E rro rs
R H R In te rru p t (IS R b it-2 )
Re c e iv e D a ta
Ho ld in g Re g is te r
( R HR)
RX F IF O
16X o r 8 X C loc k
( 8 X M O D E R egister )
R e c e iv e D a ta C har ac te r s
Da ta Bit
Va lid a tio n
E rro r
F lags in
LS R bits
4:1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XR17D154IVTR-F | 制造商:Exar Corporation 功能描述:UART 4-CH 64Byte FIFO 3.3V/5V 144-Pin LQFP T/R 制造商:Exar Corporation 功能描述:XR17D154IVTR-F |
| XR17D158 | 制造商:EXAR 制造商全称:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART |
| XR17D158_05 | 制造商:EXAR 制造商全称:EXAR 功能描述:UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART |
| XR17D158CV | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR17D158CV-0A-EVB | 功能描述:界面开发工具 Supports D158 144 ld TQFP, PCI Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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