参数资料
型号: XR68M752IL32-F
厂商: Exar Corporation
文件页数: 27/54页
文件大小: 0K
描述: IC UART FIFO 64B DUAL 32QFN
标准包装: 490
特点: *
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS422,RS485
电源电压: 1.62 V ~ 3.63 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 托盘
XR16M752/XR68M752
33
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
MCR[2]: OP1# / FIFO Rdy Enable
OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the SPR, TLR and FIFO Rdy registers. All of these registers are
accessible at address offset 0x7 when LCR≠0xBF. However, LCR = 0xBF is required to access EFR.
TABLE 12: REGISTER AT ADDRESS OFFSET 0X7
EFR[4] MCR[6] MCR[4, 2] Register at Address Offset 0x7
0
X
≠’01’
Scratchpad Register (SPR)
1
0
≠’01’
Scratchpad Register (SPR)
1
≠’01’
Trigger Level Register (TLR)
X
=’01’
FIFO Ready Register (FIFO Rdy)
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M752 is programmed to use the Xon/Xoff flow control.
MCR[6]: TCR and TLR Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the TCR and TLR registers at address offset 0x6 and 0x7, respectively. See Table 12 above
for the correct register setting to access the TLR register. See Table 13 below for the setting to access the
TCR register.
Logic 0 = Reserved (default).
Logic 1 = Enable access to the TCR and TLR registers.
TABLE 13: REGISTER AT ADDRESS OFFSET 0X6
EFR[4] MCR[6] Register at Address Offset 0x6
0
X
Modem Status Register (MSR)
1
0
Modem Status Register (MSR)
1
Trigger Control Register (TCR)
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