参数资料
型号: XRD98L59AIG-F
厂商: Exar Corporation
文件页数: 9/37页
文件大小: 0K
描述: IC CCD DIGITIZER 10BIT 28TSSOP
标准包装: 47
位数: 10
通道数: 1
电压 - 电源,模拟: 2.7 V ~ 3.6 V
电压 - 电源,数字: 2.7 V ~ 3.6 V
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-TSSOP
包装: 管件
其它名称: XRD98L59AIG-F-ND
17
Rev. 2.00
XRD98L59
D4
D3
D2
φφφφφ2 Aperture Delay
0
2.7ns (default)
0
1
4.7ns
0
1
0
6.7ns
0
1
8.7ns
1
0
10.7ns
1
0
1
12.7ns
1
0
14.7ns
1
16.7ns
Table 14. Programmable
φφφφφ2 Delays
D7
D6
D5
φφφφφ1 Aperture Delay
0
3.5ns (default)
0
1
5.5ns
0
1
0
7.5ns
0
1
9.5ns
1
0
11.5ns
1
0
1
13.5ns
1
0
15.5ns
1
17.5ns
Table 13. Programmable
φφφφφ1 Delays
SBLK and SPIX Programmable Aperture Delay
(SDI Address = 0010)
The positioning of
φ1 and φ2 from Figure 10, are opti-
mized by using a programmable aperture delay function.
φ1 and φ2 are delayed internally by the amount specified
in the serial port. SBLK delay (D7:D5) delays the
φ1
clock and SPIX delay (D4:D2) delays the
φ2 clock. The
delay is 2ns per lsb. The aperture delays t
BK and tVD are
added to the programmable aperture delay to determine
final positioning. The tables below include the t
BK and tVD
aperture delays.
The aperture delay of
φ2 also delays the output data bus
DB[9:0]. Digital output data is updated on the falling
edge of
φ2 as shown in Figure 10. Data is valid after t
DL
plus the change in
φ2 aperture delay. For example, if
D[4:2] equals 001b, then data is valid at t
DL + 2ns. (tDL
is shown in Figure 6).
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