参数资料
型号: XRT71D04IV
厂商: Exar Corporation
文件页数: 8/22页
文件大小: 0K
描述: IC JITTER ATTENUATOR 4CH 80TQFP
标准包装: 94
类型: *
PLL:
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 4:3
差分 - 输入:输出: 无/无
频率 - 最大: 44.736MHz
除法器/乘法器: 无/无
电源电压: 3.135 V ~ 5.25 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-TQFP(14x14)
包装: 托盘
XRT71D04
á
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
15
An asynchronous mapping for DS3 into STS-1 SPE is
defined for clear-channel transport of DS3 signals
that meet the DSX-3 requirements in the GR-499-
CORE.
When the input data has a rate lower than the output
data rate, the positive stuffing will occur. The stuffing
mechanism that generates the C-bits is implement-
ed in a desynchronizer that has the jitter output less
than 0.4 UIpp assuming no jitter or wander at the in-
put of the synchronizer and no pointer adjustments. A
block diagram of the Desynchronizer is shown in
The elastic store accepts the STS-1 data stream and
a gapped clock. The gaps in the input clock inhibit the
elastic store from writing all but DS3 payload data.
The bit leaking circuit stores incoming STS-1 pointer
adjustments into a queue and leaks them out of the
desynchronizer one bit at a time.
STS-Nc signal is used to transport higher rate sig-
nals. However,the digital signals that SONET carries
do not fit in the SPE perfectly.
FIGURE 8. XRT71D04 DESYNCHRONIZER BLOCK DIAGRAM
STS-N
Clock
Recovery
Descramble/
Demux
STS-1
Nth STS-1
OH
Processing
STS-1
Section &
Line Overhead
Pointer
Processing
Elastic
Store
STS-1
Dejittering &
Pointer
Adjustment
STS-1
gapped clock
STS-1
gapped clock
STS-1
reference clock
DS3 payload
(dejittered)
Stuff Control
XRT71D04
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