XRT72L50
á
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
235
4.3.6.2.8
The Detection of CP-Bit Error Interrupt
If the Detection of CP-Bit Error Interrupt is enabled, then the XRT72L50 Framer IC will generate an interrupt,
anytime the Receive DS3 Framer block has detected a CP-bit error, within the incoming DS3 data stream.
Enabling and Disabling the Detection of CP-Bit Error Interrupt:
To enable or disable the Detection of CP-Bit Error Interrupt, write the appropriate value into Bit 7 (CP-Bit Error
Interrupt Enable) within the RxDS3 Interrupt Enable Register, as illustrated below.
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of CP-Bit Error Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do all of the following.
It will assert the Interrupt Request output pin (Int) by driving it "High".
It will set Bit 7 (CP-Bit Error Interrupt Status) within the Rx DS3 Interrupt Status Register, to “1”, as indicated
below.
Whenever the Terminal Equipment encounters the Detection of CP-bit Error Interrupt, it should do the
following.
It should read contents of PMON Frame CP-Bit Error Count Register (located at 0x72 and 0x73), in order to
determine the number of CP-bit errors recently received.
4.3.6.2.9
The Receive FEAC Message - Validation Interrupt
If the Receive FEAC Message - Validation Interrupt is enabled, then the XRT72L50 Framer IC will generate an
interrupt any time the Receive FEAC Processor validates a new FEAC (Far-End Alarm & Control) Message.
In particular, the Receive FEAC Processor will validate a FEAC Message, if that same FEAC Message has
been received in 8 of the last 10 FEAC Message receptions.
Enabling/Disabling the Receive FEAC Message - Validation Interrupt
To enable or disable the Receive FEAC Message - Validation Interrupt, write the appropriate data into Bit 1
(RxFEAC Valid Interrupt Enable) within the RxDS3 FEAC Interrupt Enable/Status Register, as indicated below.
RxDS3 Interrupt Enable Register (Address = 0x12)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
00
000
RxDS3 Interrupt Status Register (Address = 0x13)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RURRUR
RUR
RURRUR
10
000
001