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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
80
2. When the Receive DS3/E3 Framer block detects the end of an LOS Condition (e.g., when the Receive
DS3/E3 Framer block detects a string 32 bits that does not contain a string of four consecutive "0’s").
The local P can determine the current state of the LOS condition by reading bit 4 of the Rx E3 Configuration
and Status Register (Address = 0x11).
NOTE: For more information in the LOS of Signal (LOS) Alarm, refer to
Bit 0 - AIS (Change in AIS Condition) Interrupt Status
This Reset Upon Read bit field will be set to "1", if the Receive DS3/E3 Framer block has detected a Change in
the AIS condition, since the last time this register was read. This bit-field will be asserted under either of the
following two conditions:
1. When the Receive DS3/E3 Framer block first detects an AIS Condition in the incoming E3 data stream.
2. When the Receive DS3/E3 Framer block has detected the end of an AIS Condition in the incoming E3 data
stream.
The local P can determine the current state of the AIS condition by reading bit 3 of the Rx E3 Configuration
and Status Register (Address = 0x11).
NOTE: For more information on the AIS Condition, refer to
2.3.4.6
Receive E3 Interrupt Status Register 2 (E3, ITU-T G.751)
Bit 3 - FERF (Change in FERF Condition) Interrupt Status
This Reset Upon Read bit will be set to '1' if the Receive DS3/E3 Framer block has detected a Change in the
Rx FERF Condition, since the last time this register was read.
This bit-field will be asserted under either of the following two conditions.
1. When the Receive DS3/E3 Framer block first detects the occurrence of an Rx FERF Condition (e.g., when
the FERF bit, within the last 3 or 5 consecutive E3 frames are set to "1").
2. When the Receive DS3/E3 Framer block detects the end of the Rx FERF Condition (e.g., when the FERF
bit, within the last 3 or 5 consecutive E3 frames are set to "0").
NOTE: For more information on the Rx FERF (Yellow Alarm) condition, refer to
Bit 2 - BIP-4 (Detection of BIP-4) Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the BIP-4 Error interrupt has occurred since the last read of
this register.
The Receive DS3/E3 Framer block will generate the BIP-4 Error interrupt if it has concluded that it has received
an errored E3 frame, from the Remote Terminal.
NOTE: Please see
Bit 1 - Framing Error Interrupt Status
This Reset-upon-Read bit-field will be set to "1" if the Framing Byte Error interrupt has occurred since the last
read of this register.
The Receive DS3/E3 Framer blockwill generate the Framing Error interrupt if it has detected an error in the
FAS (or Framing Alignment), in an incoming E3 frame.
RxE3 Interrupt Status Register 2 (Address = 0x15)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Not Used
FERF
Interrupt
Status
BIP-4
Error
Interrupt
Status
Framing
Error
Interrupt
Status
Not Used
RO
RUR
RO
0
0001
010