参数资料
型号: XRT73LC00AIVTR
厂商: Exar Corporation
文件页数: 40/61页
文件大小: 0K
描述: IC LIU STS1/DS3/E3 SGL 44TQFP
标准包装: 1,000
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 44-LQFP
供应商设备封装: 44-TQFP(10x10)
包装: 带卷 (TR)
XRT73LC00A
42
REV. 1.0.2
E3/DS3/STS-1 LINE INTERFACE UNIT
The manner that the LIU transmits Dual-Rail data to the Receiving Terminal Equipment is described below and
illustrated in Figure 25. The XRT73LC00A typically updates the data on the RPOS and RNEG output pins on
the rising edge RCLK1 (or RCLK2).
RCLK1 (or RCLK2) is the Recovered Clock signal from the incoming Received line signal. These clock signals
are typically 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications and 51.84 MHz for SONET
STS-1 applications.
If the XRT73LC00A received a positive-polarity pulse in the incoming line signal via the RTIP and RRING input
pins, then the XRT73LC00A pulses the RPOS output pin “High”. If the XRT73LC00A received a negative-
polarity pulse in the incoming line signal via the RTIP and RRING input pins, then the XRT73LC00A pulses the
RNEG output pin “High”.
Inverting the RCLK1 or RCLK2 outputs
When using the XRT73LC00A, either of the RCLK1 or RCLK2 signals can be inverted with respect to the
delivery of the RPOS and RNEG output signals to the Receiving Terminal Equipment. This feature may be
useful for those customers whose Receiving Terminal Equipment logic design is such that the RPOS and
RNEG data must be sampled on the rising edge of RCLK1 or RCLK2. Figure 26 illustrates the behavior of the
RPOS, RNEG and RCLK signals when the RCLK signal has been inverted.
FIGURE 24. THE TYPICAL INTERFACE FOR THE TRANSMISSION OF DATA IN A DUAL-RAIL FORMAT FROM THE
RECEIVE SECTION OF THE XRT73LC00A TO THE RECEIVING TERMINAL EQUIPMENT
FIGURE 25. HOW THE XRT73LC00A OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
Exar E3/DS3/STS-1 LIU
Receive
Logic
Block
RxPOS
RxNEG
RCLK1, 2
RPOS
RNEG
RCLK1, 2
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
RCLK1
RPOS
RNEG
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