参数资料
型号: XRT75L04DIV-F
厂商: Exar Corporation
文件页数: 28/98页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 4CH 176TQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 4/4
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 176-LQFP
供应商设备封装: 176-TQFP(24x24)
包装: 托盘
XRT75L04D
á
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.1
30
5.0
THE RECEIVER SECTION:
This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the
TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses.
5.1
AGC/Equalizer:
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB.
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data.
The Equalizer can either be “IN” or “OUT” by setting the REQEN_n pin “High” or “Low” (in Hardware Mode) or
setting the REQEN_n control bit to “1” or “0” (in Host Mode).
RECOMMENDATIONS FOR EQUALIZER SETTINGS:
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be left “IN” by setting the REQEN_n pin to “High” (in Hardware Mode) or setting the
REQEN_n control bit to “1” (in Host Mode).
However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse
template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet
by setting the REQEN_n pin “Low” (in Hardware Mode) or by setting the REQEN_n control bit to “0” (in Host
Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of
better jitter transfer characteristics.
NOTE: The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN_n = “HIGH”),
regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable
loss at Industrial Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the
resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a “1” to
the RxMON_n bits in the control register or by setting the RxMON pin (pin 69) “High”.
5.1.1
Interference Tolerance:
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/
STS1. Figure 18 shows the set up for E3.
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Test Equipment
Pattern Generator
2 23 -1 PRBS
Sine Wave
Generator
N
S
Cable Simulator
DUT
XRT75L04D
Attenuator
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
相关PDF资料
PDF描述
XRT75L04IV-F IC LIU E3/DS3/STS-1 4CH 176LQFP
XRT75L06DIB-F IC LIU E3/DS3/STS-1 6CH 217BGA
XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
XRT75R03DIV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
XRT75R03IV-F IC LIU E3/DS3/STS-1 3CH 128LQFP
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XRT75L04DIVTR-F 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel
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