参数资料
型号: XRT75L04DIV-F
厂商: Exar Corporation
文件页数: 93/98页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 4CH 176TQFP
标准包装: 72
类型: 线路接口装置(LIU)
驱动器/接收器数: 4/4
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 176-LQFP
供应商设备封装: 176-TQFP(24x24)
包装: 托盘
á
XRT75L04D
REV. 1.0.1
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
89
that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3
data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame
synchronization within 50ms" after APS has been initiated."
The LIU was designed such that the DS3 signals that it receives from a SONET Mapper device and processes
will comply with the Category I Intrinsic Jitter requirements per Telcordia GR-253-CORE.
Reference 1 documents some APS Recovery Time testing, which was performed to verify that the Jitter
Attenuator blocks (within the LIU) device that permit it to comply with the Category I Intrinsic Jitter
Requirements (for DS3 Applications) per Telcordia GR-253-CORE, do not cause it to fail to comply with the
"APS Completion Time" requirements per Section 5.3.3.3 of Telcordia GR-253-CORE.
However, Table 3
presents a summary of some APS Recovery Time requirements that were documented within this test report.
Table 3,
NOTE: The APS Completion (or Recovery) time requirement is 50ms.
Configuring the LIU to be able to comply with the SONET APS Recovery Time Requirements of 50ms
Quite simply, the user can configure a given Jitter Attenuator block (associated with a given channel) to (1)
comply with the "APS Completion Time" requirements per Telcordia GR-253-CORE, and (2) also comply with
the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications) by making
sure that Bit 4 (SONET APS Recovery Time Disable Ch_n), within the Jitter Attenuator Control Register is set
to "0" as depicted below.
TABLE 24: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET
DS3 PPM OFFSET (PER W&G ANT-20SE)
MEASURED APS RECOVERY TIME (PER LOGIC ANALYZER)
-99 ppm
1.25ms
-40ppm
1.54ms
-30 ppm
1.34ms
-20 ppm
1.49ms
-10 ppm
1.30ms
0 ppm
1.89ms
+10 ppm
1.21ms
+20 ppm
1.64ms
+30 ppm
1.32ms
+40 ppm
1.25ms
+99 ppm
1.35ms
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7BIT 6BIT 5
BIT 4BIT 3BIT 2BIT 1BIT 0
Unused
SONET APS
Recovery
Time Disable
Ch_n
JA RESET
Ch_n
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
相关PDF资料
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XRT75L04IV-F IC LIU E3/DS3/STS-1 4CH 176LQFP
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XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
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