参数资料
型号: XRT75L06DIB-F
厂商: Exar Corporation
文件页数: 100/103页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 6CH 217BGA
标准包装: 60
类型: 线路接口装置(LIU)
驱动器/接收器数: 6/6
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 217-BBGA
供应商设备封装: 217-BGA(23x23)
包装: 托盘
xr
XRT75L06D
REV. 1.0.4
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
92
CROSS-CHECKING OUR DATA
Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
This amount to a period of (2160/51.84MHz) = 41,667ns.
In a period of 41, 667ns, the LIU (when configured to operate in the DS3 Mode), will output a total (41,667ns
x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE LIU
Whenever the LIU is configured to operate in a "SONET De-Sync" application, the device will accept a
continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the LIU (which will be configured to operate in the "DS3" Mode) will
output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements -
per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure 72.
7.8.3
How does the LIU permit the user to comply with the SONET APS Recovery Time
requirements of 50ms (per Telcordia GR-253-CORE)?
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or
less. Many of our customers interpret this particular requirement as follows.
"From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which
is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the
"high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities
FIGURE 71. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
FIGURE 72. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION
PATTERN A
PATTERN B
DS3 to STS-N
Mapper/
Demapper
IC
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TPDATA_n input pin
TCLK_n input
De-Mapped (Gapped)
DS3 Data and Clock
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XRT75L06IB-F IC LIU E3/DS3/STS-1 6CH 217BGA
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