参数资料
型号: XRT75R03DIVTR
厂商: Exar Corporation
文件页数: 107/135页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 3CH 128LQFP
标准包装: 750
类型: 线路接口装置(LIU)
驱动器/接收器数: 3/3
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 带卷 (TR)
XRT75R03D
69
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02
Channel 1 Address Location = 0x0A
Channel 2 Address Location = 0x12
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of FL
Condition
Interrupt Status
Ch_n
Change of LOL
Condition
Interrupt Status
Ch_n
Change of LOS
Condition
nterrupt Status
Ch_n
Change of DMO
Condition
Interrupt Status
Ch_n
R/O
RUR
0
BIT NUMBER
NAME
TYPE
DEFAULT
VALUE
DESCRIPTION
7 - 4
Unused
R/O
0
3
Change of FL Con-
dition Interrupt Sta-
tus
RUR
0
Change of FL (FIFO Limit Alarm) Condition Interrupt Status
- Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of FL Condition Interrupt (for Channel 0) has
occurred since the last read of this register.
0 - Indicates that the Change of FL Condition Interrupt has
NOT occurred since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the FIFO
Alarm condition by reading out the contents of Bit 3
(FL Alarm Declared) within the Alarm Status
Register.
2
Change of LOL Con-
dition Interrupt Sta-
tus
RUR
0
Change of Receive LOL (Loss of Lock) Condition Interrupt
Status - Ch 0:
This RESET-upon-READ bit-field indicates whether or not
the Change of Receive LOL Condition Interrupt (for Chan-
nel 0) has occurred since the last read of this register.
0 - Indicates that the Change of Receive LOL Condition
Interrupt has NOT occurred since the last read of this regis-
ter.
1 - Indicates that the Change of Receive LOL Condition
Interrupt has occurred since the last read of this register.
NOTE:
The user can determine the current state of the
Receive LOL Defect condition by reading out the
contents of Bit 2 (Receive LOL Defect Declared)
within the Alarm Status Register.
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