参数资料
| 型号： | XRT8020IL-F |
| 厂商： | Exar Corporation |
| 文件页数： | 4/12页 |
| 文件大小： | 0K |
| 描述： | IC CLK MULTIPLR LVDS 16QFN |
| 标准包装： | 490 |
| 类型： | 时钟/频率倍增器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH |
| 输入： | 晶体 |
| 输出： | LVDS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 675MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（4x4） |
| 包装： | 散装 |
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
11
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet November 2003.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISIONS
P1.0.1 Accumulated output jitter in electrical specs changed from 25 ps @ 624MHz to 20 @ 622Mhz and
TBD to 20 ps @312Mhz. Pin 9 has internal a pull-down resistor instead of pull-up. Table 1 FS0 and FS1 bit
pattern changed.
P1.0.2 Changed typical jitter to 6ps and changed package to QFN
P1.0.3 Corrected package dimension dimension "e" to 0.65 mm BSC. Updated electrical tables. Added de-
scriptive sections on Calibration, Crystal Selection and Data and Plots.
1.0.0 Final Release. Added intrinsic jitter measurements to the electrical characteristics.
1.0.1 Changed the page numbering. Changed the QLP to QFN in the Features on page 1.
1.0.2 Changed the Package Drawing and Dimensions.
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