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参数资料
| 型号： | XRT81L27IV |
| 厂商： | Exar Corporation |
| 文件页数： | 15/30页 |
| 文件大小： | 0K |
| 描述： | IC LIU EI 7CH 3.3V 128TQFP |
| 标准包装： | 72 |
| 应用： | DECT |
| 接口： | 串行 |
| 电源电压： | 3.3V |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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XRT81L27
á
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
20
nal samples this input pin on the falling edge of the
TCLK clock signal and encodes it into the appropriate
bipolar line signal across the TTIP and TRING output
pins.In this mode the Transmit Logic Block ignores
the TNEG input pin.
Figure 9 illustrates the behavior of the TPOS and
TCLK signals when the Transmit Logic Block has
been configured to accept Single-Rail data from the
Terminal Equipment.
2.1.3
TClk input
TCLK is a clock input signal of 2.048 MHz. The global
signal TClkP can be used to invert the polarity of the
sampling clock relative to the TClk input pin for both
SD and DR modes.
2.2
THE ENCODER BLOCK
The purpose of the Encoder Block is to aid in the
Clock Recovery process at the Remote Terminal
Equipment by ensuring an upper limit on the number
of consecutive zeros that can exist in the line signal.
2.2.1
HDB3 Encoding
When the Encoder is enabled (by the global CODE
bit set and Single-Rail mode selected), it parses
through and searches the Transmit Data Stream from
the Transmit Logic Block for the occurrence of four (4)
consecutive zeros (“0000”). If the HDB3 Encoder
finds an occurrence of four consecutive zeros, it then
substitutes these four “0’s” with either a “000V” or a
“B00V” pattern to insure that an odd number of bipo-
lar pulses exist between any two consecutive viola-
tion pulses.
“B” represents a Bipolar pulse that is compliant with
the Alternating Polarity requirements of the AMI (Al-
ternate Mark Inversion) line code and “V” represents
a bipolar Violation (e.g., a bipolar pulse that violates
the Alternating Polarity requirements of the AMI line
code).
Figure 10 illustrates the HDB3 Encoder at work with
two separate strings of four (or more) consecutive ze-
ros showing a “000V and a “B00V” usage
2.3
THE MUX BLOCK
The MUX block accepts data inputs from the Encoder
block and the Remote loopback. Under control of the
channel control bits it will select the desired bit stream
and send it to the timing control block. Remote loop-
back provides a path for the XRT81L27 to send re-
ceived data back over the Transmit line (TTIP -
TRING) to the “other” end of the Timing Control block
FIGURE 9. SINGLE-RAIL DATA FROM THE TERMINAL
TCLK
TPDATA
Data
1
0
FIGURE 10. HDB3 ENCODING
TClk
TPOS
SR data
Encoded
PDATA
Encoded
NDATA
Line signal
100
1
01
00
1
0
00
1
0
1
01
1
0
BV
0
V
0
00
1
00
01
0
00
0
1
11
0
0000
0
10
0
01
1
10
1
0
10
1
0
1
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相关代理商/技术参数 |
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|---|---|
| XRT81L27IV-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XR-T8205CP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telephone Ringer |
| XR-T8205P | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telephone Ringer |
| XRT82D20 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
| XRT82D20_06 | 制造商:EXAR 制造商全称:EXAR 功能描述:SINGLE CHANNEL E1 LINE INTERFACE UNIT |
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