参数资料
| 型号： | XRT83SH38IB |
| 厂商： | Exar Corporation |
| 文件页数： | 22/78页 |
| 文件大小： | 0K |
| 描述： | IC LIU SH T1/E1/J1 8CH 225BGA |
| 标准包装： | 84 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 8/8 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 225-BGA |
| 供应商设备封装： | 225-BGA（19x19） |
| 包装： | 托盘 |
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XRT83SH38
26
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
monitor the 16-bit LCV counter by programming the appropriate global register, the LCV/OFD will be set to a
"1" if the counter saturates.
3.3
Receive Jitter Attenuator
The receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered
clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit.
If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read
and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter
attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition
occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer’s position is outside the 2-
Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the bandwidth is
programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a
clock delay equal to of the FIFO bit depth.
NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the transmit path has
a dedicated jitter attenuator to smooth out the gapped clock. See the Transmit Section of this datasheet.
3.4
HDB3/B8ZS Decoder
In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any
block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite
polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with OOOVBOVB. If the
HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is
output to RPOS.
3.5
RPOS/RNEG/RCLK
The digital output data can be programmed to either single rail or dual rail formats. Figure 13 is a timing
diagram of a repeating "0011" pattern in single-rail mode. Figure 14 is a timing diagram of the same fixed
pattern in dual rail mode.
FIGURE 13. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
FIGURE 14. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN
RCLK
RPOS
00
0
1
RCLK
RPOS
00
0
1
RNEG
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SH38IB-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL216 | 制造商:EXAR 制造商全称:EXAR 功能描述:16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL216_06 | 制造商:EXAR 制造商全称:EXAR 功能描述:16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SL216ES | 功能描述:外围驱动器与原件 - PCI 16 CH E1 LIU SH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL216IB | 功能描述:接口 - 专用 RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
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