参数资料
型号: XRT83SH38IB
厂商: Exar Corporation
文件页数: 7/78页
文件大小: 0K
描述: IC LIU SH T1/E1/J1 8CH 225BGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 225-BGA
供应商设备封装: 225-BGA(19x19)
包装: 托盘
XRT83SH38
12
REV. 1.0.7
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
JITTER ATTENUATOR
CLOCK SYNTHESIZER
PCLK/ATAOS
T13
I
Synchronous Microprocessor Clock/Automatic Transmit All Ones
Host Mode
This synchronous input clock is used as the internal master clock to the microproces-
sor interface when configured for in a synchronous mode.
Hardware Mode
This pin is used select an all ones signal to the line interface through TTIP/TRING any
time that a loss of signal occurs. This feature is avaiable in Host mode by program-
ming the appropriate global register.
NOTE: Internally pulled “Low” with a 50k
resistor.
INT
L16
O
Interrupt Output/Turns Ratio Select (External Impedance Mode)
Host Mode
This signal is asserted "Low" when a change in alarm status occurs. Once the status
registers have been read, the interrupt pin will return "High". GIE (Global Interrupt
Enable) must be set "High" in the appropriate global register to enable interrupt gen-
eration.
NOTES:
1. This pin is an open-drain output that requires an external 10K
pull-up
resistor.
2. Internally pulled “Low” with a 50k
resistor.
SIGNAL
NAME
BGA
LEAD #
TYPE
DESCRIPTION
JASEL0
JASEL1
A14
B13
I
Jitter Attenuator Select Pins Hardware Mode
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive
path or to disable it.
NOTE: These pins are internally pulled “Low” with 50k
resistors.
SIGNAL NAME
BGA
LEAD #
TYPE
DESCRIPTION
MCLKOUT
H1
O
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1
rate based upon the mode of operation.
SIGNAL NAME
BGA
LEAD
#
TYPE
DESCRIPTION
Disabled
Transmit
Receive
JA Path
JA BW Hz
--------
32/32
64/64
FIFO Size
-----
3
-----
10
1.5
0
1
JASEL1
0
1
0
1
JASEL0
T1
E1
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