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参数资料
型号： XRT86VL30IV-F
厂商： Exar Corporation
文件页数： 160/175页
文件大小： 0K
描述： IC FRAMR/LIU T1/E1/J1 QD 128LQFP
标准包装： 72
控制器类型： T1/E1/J1 调帧器，LIU
电源电压： 3.3V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 128-LQFP
供应商设备封装： 128-LQFP（14x20）
包装： 托盘
其它名称： 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
80
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3-0
TxCond(3:0)
R/W
0000
Transmit Channel Conditioning for Timeslot 0 to 23
These bits allow the user to substitute the input PCM data (Octets 0-23)
with internally generated Conditioning Codes prior to transmission to the
remote terminal equipment on a per-channel basis. The table below pre-
sents the different conditioning codes based on the setting of these bits.
Register address 0x0300 represents time slot 0, and address 0x0317 repre-
sents time slot 23.
TABLE 66: TRANSMIT CHANNEL CONTROL REGISTER 0-23 (TCCR 0-23)
HEX ADDRESS: 0X0300 TO 0X0317
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
TXCOND[1:0]
CONDITIONING CODES
0x0 / 0xE
Contents of timeslot octet are unchanged.
0x1
All 8 bits of the selected timeslot octet are inverted (1’s
complement)
OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF
0x2
Even bits of the selected timeslot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA
0x3
Odd bits of the selected time slot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0x55
0x4
Contents of the selected timeslot octet will be substituted
with the 8 -bit value in the Transmit
Programmable User Code Register (0x0320-0x0337),
0x5
Contents of the timeslot octet will be substituted with the
value 0x7F (BUSY Code)
0x6
Contents of the timeslot octet will be substituted with the
value 0xFF (VACANT Code)
0x7
Contents of the timeslot octet will be substituted with the
BUSY time slot code (111#_####), where ##### is the
Timeslot number
0x8
Contents of the timeslot octet will be substituted with the
MOOF code (0x1A)
0x9
Contents of the timeslot octet will be substituted with the
A-Law Digital Milliwatt pattern
0xA
Contents of the timeslot octet will be substituted with the
-Law Digital Milliwatt pattern
0xB
The MSB (bit 1) of input data is inverted
0xC
All input data except MSB is inverted
0xD
Contents of the timeslot octet will be substituted with the
PRBS X15 + X 14 + 1/QRTS pattern
NOTE: PRBS X15 + X 14 + 1 or QRTS pattern depends on
PRBSType selected in the register 0x0123 - bit 7
0xF
D/E time slot - The TxDE[2:0] bits in the Transmit Signal-
ing and Data Link Select Register (0x010A) will determine
the data source for D/E time slots.
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XRT86VL30IV-F 制造商:Exar Corporation 功能描述:T1/E1 Framer Combo IC
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