参数资料
型号: XRT86VL30IV-F
厂商: Exar Corporation
文件页数: 72/175页
文件大小: 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 128LQFP
标准包装: 72
控制器类型: T1/E1/J1 调帧器,LIU
电源电压: 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 托盘
其它名称: 1016-1485
XRT86VL30IV-F-ND
XRT86VL30
158
REV. 1.0.1
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 134: LIU CHANNEL CONTROL CABLE LOSS REGISTER (LIUCCCCR)
HEX ADDRESS: 0X0F07
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
RO
0
6
Reserved
RO
0
5-0
CLOS[5:0]
RO
0
Cable Loss [5:0]:
These bits represent the six bit receive selective equalizer setting
which is also a binary word that represents the cable attenuation
indication within ±1dB.
CLOS5_n is the most significant bit (MSB) and CLOS0_n is the
least significant bit (LSB).
NOTE: In RxSYNC (Sect 13) mode, ExLOS must be configured (this
will set the DLOS to 4,096 bits which does not meet G.775).
However, the CLOS bits can be used to meet the DLOS
requirements of G.775 with a simple software procedure. To
meet G.775, simply choose a desired value of attenuation
(For example: 12dB) to monitor in this register for RLOS
within a time period of 175 Clock Cycles +/-75. The internal
RLOS alarm should be masked unless ExLOS is being
used. For more details, please contact the factory.
TABLE 135: LIU CHANNEL CONTROL ARBITRARY REGISTER 1 (LIUCCAR1)
HEX ADDRESS: 0X0F08
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg1
R/W
0
Arbitrary Transmit Pulse Shape, Segment 1:
These seven bits form the first of the eight segments of the transmit
shape pulse when the XRT86VL30 is configured in “Arbitrary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0F00.
TABLE 136: LIU CHANNEL CONTROL ARBITRARY REGISTER 2 (LIUCCAR2)
HEX ADDRESS: 0X0F09
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
Reserved
R/W
0
6-0
Arb_Seg2
R/W
0
Arbitrary Transmit Pulse Shape, Segment 2
These seven bits form the second of the eight segments of the
transmit shape pulse when the XRT86VL30 is configured in “Arbi-
trary Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pulse in signed magnitude format with Bit 6 as the sign bit and
Bit 0 as the least significant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0F00.
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