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| 型号： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫参考平台硬件设计手册 |
| 文件页数： | 11/24页 |
| 文件大小： | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 18 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
NOTE: Not all processors support all options. Additionally, since the Yellowknife does
not directly support clock speeds below 50 MHz, many of the PLL settings are not directly
usable.
4.1.3 MPC106 Frequency Selection
Jumpers J57, J59, J58 and J60 are used to set the ratio of the PCI bus clock to the proces-
sor bus clock, so the MPC106 can communicate in sync. with both. The core speed is
always an integer or half-integer multiple of the “Bus Clock” speed selected with the Sys-
tem Frequency jumpers.
4.1.4 COP Function Jumper
Jumper J39 must be installed to allow full operation of the COP processor debugging fea-
out
IN
3X
50 ... 83
150 ... 250
out
IN
out
5.5X
out
IN
out
IN
4X
50 ... 66
200 ... 266
out
IN
out
5X
50
250
out
IN
out
IN
out
6X
out
IN
3.5X
50 ... 75
175 ... 262
out
OFF
Table 7: Processor Clock Settings
J35
CP0
J36
CP1
J
38
CP2
J40
CP3
PLL
PCI
Clock
Bus
Clock
IN
out
1X
33
IN
out
IN
1X
16 ... 25
IN
out
BYPASS
IN
out
IN
2X
33
66
IN
out
IN
out
2X
16 ... 25
33 ... 50
IN
out
IN
2.5X
33
83
IN
out
2.5X
16 ... 20
40 ... 50
out
IN
3X
25 ... 33
75 ... 100
out
IN
out
3X
16
50
out
IN
out
IN
out
IN
out
IN
out
IN
out
IN
out
OFF
Table 6: Processor Clock Settings
J35
CP0
J36
CP1
J
38
CP2
J40
CP3
PLL
Bus
Clock
Core
Clock
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