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| 型号： | YKNIFEX4HW |
| 英文描述： | IC APEX 20KE FPGA 100K |
| 中文描述： | 耶洛奈夫参考平台硬件设计手册 |
| 文件页数： | 23/24页 |
| 文件大小： | 186K |
| 代理商： | YKNIFEX4HW |
Yellowknife X4 Hardware Reference Manual
Page 7 /22
Motorola Inc.
Unrestricted Distribution Permitted
98 Feb 20
2.4 L2 Cache Memory
Cache for the YK system is provided through an on-board “TAGRAM” memory and a pair
of high-speed SRAM memories. The IDT71216 provides the cache tag RAM and address
comparator for the cache module. The SRAM parts are selected for the maximum speed
available; if cache is desired, the SRAM parts must match the speed of the processor and
SDRAM data bus.
FIGURE 2. Cache Architecture
CHANGES: X4 replaces the L2 COAST socket with on-board 100-pin TQFP SRAM.
This is both cheaper and faster, allowing faster operation (83 MHz or greater). Since the
cache is xed at 512K, jumpers are no-longer needed.
2.5 Power Supply
Up to 7A of power is supplied to the processor’s core logic, using a 5-bit DAC-trimmed
switching regulator. The regulator is contained on a daughter-card called the Voltage Reg-
ulator Module (VRM). Using the VID(4:0) control signals present on all second-genera-
tion modules, the appropriate voltage level for the processor is automatically selected.
This voltage may range anywhere from 1.3V to 3.6V.
Uninstalled jumpers on the PCB may be installed to allow trimming the voltage for test
purposes. To trim the voltage, cut the top-level trace between pins 1 and 2 and install
three-position “Berg” headers at locations J45, J46, J47, J55, and J56. Once done, the fol-
lowing controls are possible:
Table 1: Optional VID Control
J45
VID4
J46
VID3
J47
VID2
J48
VID1
J49
VID0
Result
1-2
Interposer controls voltage settings.
out
No Interposer Installed
out
2-3
2.10V Core
IDT
TAGRAM
PowerPC
MPC60X
Grackle
MPC106
HIT
IDT
TAGRAM
Motorola
SRAM
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