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参数资料
| 型号： | YMF721-S |
| 元件分类： | 音频合成 |
| 英文描述： | SPEECH SYNTHESIZER, PQFP100 |
| 封装： | SQFP-100 |
| 文件页数： | 6/41页 |
| 文件大小： | 324K |
| 代理商： | YMF721-S |
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YMF721
July 10, 1997
- 14 -
6. Registers
6-1. MPU401 compatible register
MPU401 is a generally used interface for controlling MIDI devices on the personal computer. I/O
addresses that are compatible with MPU401 are as follows.
MPU_Base+ 0
(W/R)
MIDI Data transmit/acknowledge port
MPU_Base + 1
(R)
Status Register port
MPU_Base + 1
(W)
Command Register port
MIDI Data Write Port (WO):
port
D7
D6D5D4D3D2D1D0
MPU_Base + 0
MIDI Data
MIDI Data...
Port for writing MIDI data (transmitting). Transmission of the
data must be carried out while the transmitter of MIDI data is
watching the state of DRR bit of the status register. An interrupt
occurs in the internal processor when MIDI data has been
written into the register. Since YMF721 (OPL4-ML2) has no
output signal for transmitting MIDI data, the MIDI data written
into this register is used to operate internal Wavetable
synthesizer.
MPU Acknowledge Port (RO):
port
D7
D6D5D4D3D2D1D0
MPU_Base + 0
“1”
“0”
Sends acknowledge for the operation of MPU401.
When operation of the MPU401 is normal, "FEh" is read from this port.
Status Register Port (RO):
port
D7
D6D5D4D3D2D1D0
MPU_Base + 1
DSR
DRR
“1”
DSR...
This bit is "1" when reading the acknowledge from MPU401.
This bit is "0" when writing commands.
DRR...
This bit is "1" while MIDI data is being written into MPU Data
Write port (MPU Base+0). This bit is "0" when the MIDI data
can be written into the MPU Data Write port. Do not write
MIDI data when this bit is "1".
Default : BFh
Command Register Port (WO):
port
D7
D6D5D4D3D2D1D0
MPU_Base + 1
COMMAND Data
COMMAND Data...
The data written into this register is ignored. DSR bit is set to
"0" when data is written into this register.
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