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参数资料
| 型号： | YMF721-S |
| 元件分类： | 音频合成 |
| 英文描述： | SPEECH SYNTHESIZER, PQFP100 |
| 封装： | SQFP-100 |
| 文件页数： | 9/41页 |
| 文件大小： | 324K |
| 代理商： | YMF721-S |
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YMF721
July 10, 1997
- 17 -
6-4. Control/Status register
I/O port for Control/Status register is described here.
Control/Status Port (R/W):
port
D7
D6D5D4D3D2D1D0
OPL_Base + 7(W)
PDY
PDX
-
MPR
“0”
“1”
OPL_Base + 7(R)
PDY
PDX
-
BSEL
-
RESP
GBUSY
GDRQ
PDY, PDX...
YMF721 recovers from power down mode by using the
following sequence.
PDY=“1”, PDX=“0”
wait time (in case of using crystal oscillation)
PDY=“0”, PDX=“0”
D7 and D6 bits of Status register become "1" during power
down mode. In this state, oscillation of clock can be confirmed
by monitoring the status bit during power down mode in/out
sequence.
MPR...
Setting this bit to "0" initializes internal processor. Default
value of this bit is "1".
BSEL...
This bit shows connection of internal bus of YMF721(OPL4-
ML2). Default value of this bit is "1".
“1” : Connecting synthesizer and internal processor
“0” : Connecting synthesizer and ISA bus
RESP...
Indicates that a response to a command has been received.
GBUSY...
Flag bit that indicates if data can be written into Command write
register.
“1” : BUSY
“0” : Data can be written
GDRQ...
Flag bit that indicates if data can be read from Response
register.
“1” : READY
“0” : Reading is inhibited
Default : (00x1 x000)b0
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| YMF724 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:high performance audio controller for the PCI Bus |
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