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参数资料
| 型号： | YMF781-SZ |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, PLASTIC, SQFP-100 |
| 文件页数： | 2/14页 |
| 文件大小： | 739K |
| 代理商： | YMF781-SZ |
YMF781
10
·
Asynchronous Serial Interface （UART）
Ｉ
tem
Symbol
Ｍ
in.
Ｔ
yp.
Ｍ
ax.
Ｕ
nit
Transfer Frequency (Baud rate: fixed to x16)
1 / TRXD
9
144
kHz
RXD allowable frequency error (*1)
-2
+2
%
Conditions: TOP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) In the case of 10 bits including the start bit and the stop bit.
·
External Memory Interface
Ｉ
tem
Symbol
Ｍ
in.
Ｔ
yp.
Ｍ
ax.
Ｕ
nit
Data (D) Set-up time
TDS
10
ns
Data (D) Hold time
TDH
10
ns
Address (A) Output Delay time
TAD
40
ns
Control Signal Output Delay time (*1)
TCTLD
40
ns
Data (D) Output Delay time
TDD
80
ns
Data (D) Output turn-on time
TDT
20
ns
Conditions: TOP= -40 to 85℃, VDD= 3.0 to 3.6V, VDDC= 3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) LBN/LWRN, UBN/UWRN, WRN, RDN, and CS*N
※
Note that the output timing of LWRN, UWRN, and WRN differs in the access time of 3 clocks or less and that of 4 clocks or more.
A[21:0]
Internal Master Clock
MCK
TAD
D[15:00]
(Output)
LWRN, UWRN,
WRN（3clock or less）
TCTLD
D[15:00]
(Input)
TAD
TDD
TDH
TDS
LWRN, UWRN,
WRN（4clock or more）
TCTLD
TDT
Access time 2 to 9 clocks (variable)
LBN, UBN,
CS*N, RDN
TCTLD
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