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参数资料
| 型号： | YMU762C-QZ |
| 元件分类： | 音频合成 |
| 英文描述： | TONE/MUSIC SYNTHESIZER, PQCC32 |
| 封装： | LEAD FREE, PLASTIC, QFN-32 |
| 文件页数： | 14/17页 |
| 文件大小： | 529K |
| 代理商： | YMU762C-QZ |
YMU762C
6
Outline of blocks
This section outlines functions of blocks contained in this device and flow of signals.
C
P
U
Int
erf
ac
e
FIFO
Sequencer
Synthesizer
DAC
EQ
Amp
Speaker
Amp
Headphone
Output
Instantaneous write path
Delayed write path
Instantaneous read path
Clock Input
Clock
Generator
LED Control
Vibrator Control
In
te
rfac
eR
eg
ister
Int
erm
ed
ia
te
R
egi
ste
r
Control
Register
ROM/
SRAM
CPU interface
CPU interface is an 8-bit parallel type.
It assumes that a total of 13 pins of 4 control signal (/WR, /RD, /CS, A0 pin), 8 Data bus (D0 to D7) and 1 Interruption
pin (/IRQ) are connected to external microcomputer.
This block is to control the writing and reading of data by the input polarity of control signal.
Interface register
This register is to access directly form the external CPU. There are 2 bytes space.
Intermediate register
This register is to access through the Interface register.
“Control register”, which describes below, can be accessed through this register. This register is called “ Intermediate
register” since this exists in the middle of Interface register and Control register. In Intermediate register, there are
some registers to control various functions.
Control register, ROM/SRAM
These register and memory are to be accessed through Instantaneous path and Sequencer path.
In Control register, there is a register to control the following synthesizer mainly.
The voice parameter for FM (GM 128 voices + DRUM 40 voices) and Wave data for Wave Table are built in ROM.
SRAM is used at the download of arbitrary FM voice parameter and Wave data for Wave Table.
Moreover, it is used as storing buffer at the stream playback of PCM/ADPCM.
FIFO
This is abbreviation of “First In First Out” and means that the memory which data is read in order of written.
There are 2 paths to write into FIFO in Intermediate register.
“Instantaneous write path” is to access Control register and ROM/RAM immediately. And “Delayed write path” is to
access Control register after managing time through the sequencer.
FIFO size of Instantaneous path is 64-byte and its size of Delayed path is 512-byte.
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相关代理商/技术参数 |
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| YMW025 | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:2.50mm PITCH CONNECTOR |
| YMW025-02R | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:2.50mm PITCH CONNECTOR |
| YMW025-03R | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:2.50mm PITCH CONNECTOR |
| YMW025-04R | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:2.50mm PITCH CONNECTOR |
| YMW025-05R | 制造商:YEONHO 制造商全称:YEONHO ELECTRONICS 功能描述:2.50mm PITCH CONNECTOR |
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