参数资料
型号: YMU762C-QZ
元件分类: 音频合成
英文描述: TONE/MUSIC SYNTHESIZER, PQCC32
封装: LEAD FREE, PLASTIC, QFN-32
文件页数: 15/17页
文件大小: 529K
代理商: YMU762C-QZ
YMU762C
7
Sequencer
This is to interpret the contents of data which was written into Delayed write path.
The structure of data which is written into Delayed write path is “Time information data + Register setting data”.
Sequencer interprets the data of Time information and counts the time, and sets register after the time passes.
Generally, “Music data” is written into Delayed write path. It has a role to interpret the contents of music data and to
control the synthesizer after sequencer, and then to replay the music.
Synthesizer
This device, contains a Polyphonic synthesizer that is FM+Wave Table stereophonic hybrid system adopted, generates
up to 40 tones.
The FM synthesizer has two operation modes; “16-Voice 4 operation mode” and “32-Voice 2 operation mode” which
can be changed to each other freely (except during tone generation).
Since waveform for FM operation can be set arbitrarily, it is able to create more complex voices than that in
conventional devices.
Wave Table synthesizers is able to generate eight voices simultaneously, and supports 8 bit PCM and 4 bit ADPCM
data format. The sampling frequency is 48 kHz. Stream replaying is also available.
DAC
Converts digital signal from a synthesizer into analog signal. The data length is 16bit.
Headphone output
There is Stereo analog output for Headphone. The monaural output is also possible.
EQ amplifier
The change of Filter characteristic and Gain is possible by adjusting the resistor of external parts and the Capacitor.
Speaker amplifier
A speaker amplifier of which maximum out is 580 mW at SPVDD=3.6V is built in this device. There is a Volume
which adjusts output level in the first part of amplifier.
LED, Vibrator control
LED and vibrator can be controlled synchronizing with a play. Control asynchronous with play is also possible.
Clock generating block
This devices supports clock input ranging from 2 MHz to 27 MHz. (Stop = 0 Hz is possible at power down.)
It is a block to create clock which is needed inside of LSI in the PLL.
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