
YMU762C
12
● CPU interface 1 (In the case of IOVDD≧2.65V)
Condition (Common to Write cycle and Read cycle.)
TOP=-20 85°C, VDD=2.65 3.30V, IOVDD=2.65 VDD[V], Capacitor load= 50pF
IOH= -1.0mA, IOL= +1.0mA (Applies to D0 D7 pins.)
Measurement point : VIH= 0.7 × IOVDD, VIL=0.2 × IOVDD, VOH=0.8 × IOVDD, VOL=0.2 × IOVDD
(Write cycle)
Item
Symbol
Min
Max.
Unit
Address setup time
TADS
50
ns
Address hold time
TADH
0
ns
Chip select setup time
TCSS
50
ns
Chip select hold time
TCSH
0
ns
Write pulse width
TWW
50
ns
Data setup time
TWDS
30
ns
Data hold time
TWDH
0
ns
(Read cycle)
Item
Symbol
Min
Max.
Unit
Address setup time
TADS
80
ns
Address hold time
TADH
0
ns
Chip select setup time
TCSS
80
ns
Chip select hold time
TCSH
0
ns
Read pulse width
TRW
80
ns
Read data access time
TACC
70
ns
Data hold time
TRDH
0
30
ns
● CPU interface 2 (In the case of IOVDD < 2.65V)
Condition (Common to Write cycle and Read cycle.)
TOP=-20 85°C, VDD=2.65 3.30V, IOVDD=1.65 less than 2.65V, Capacitor load= 50pF
IOH= -0.2mA, IOL= +0.2mA (Applies to D0 D7 pins.)
Measurement point : VIH= 0.65 × IOVDD, VIL=0.35 × IOVDD, VOH=0.65 × IOVDD, VOL=0.35 × IOVDD
(Write cycle)
Item
Symbol
Min
Max.
Unit
Address setup time
TADS
50
ns
Address hold time
TADH
0
ns
Chip select setup time
TCSS
50
ns
Chip select hold time
TCSH
0
ns
Write pulse width
TWW
50
ns
Data setup time
TWDS
50
ns
Data hold time
TWDH
0
ns
(Read cycle)
Item
Symbol
Min
Max.
Unit
Address setup time
TADS
80
ns
Address hold time
TADH
0
ns
Chip select setup time
TCSS
80
ns
Chip select hold time
TCSH
0
ns
Read pulse width
TRW
80
ns
Read data access time
TACC
80
ns
Data hold time
TRDH
0
30
ns