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参数资料
| 型号： | YSS932 |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封装： | SQFP-128 |
| 文件页数： | 23/24页 |
| 文件大小： | 335K |
| 代理商： | YSS932 |
YSS932
8
FUNCTION DESCRIPTION
YSS932 consists of three blocks; the Main DSP block where AC-3 / Pro Logic II / DTS decoding is executed,
the Sub DSP block where various sound field effects are added and the SPDIF receiver (DIR) block.
The Sub DSP is a 8 channel input / 8 channel output programmable DSP exclusively for sound field
processing. It can apply such effects as simulation surround, output configuration and virtual surround. In
addition, with SRAM or DRAM connected, it can produce reverberation for 2.7 seconds or longer. By using
this function, it is possible to simulate various sound fields such as a hall or a church.
The SPDIF receiver (DIR) can handle the digital audio interface format input signals of the sampling
frequency 32kHz through 96kHz.
Note)
If adopting some technology owned by another company is desired for use in Sub DSP block, note that a separate
contract may be required between the owner of that technology and the user with respect to adoption of the
technology.
PIN DESCRIPTION
1) DIR Block
1-1) Digital audio interface signal input
l DDIN0-3
Input digital audio interface format signal (DAIF signal) into these pins. Then the signal selected by control
register DDINSEL0, 1 is input to the DIR block.
As the pull-up resistors are not built in, connect the unnecessary pins to VSS.
Also, DDIN1, 2, 3 are served as IPORT5, 6, 7. If they are not used as DDIN input pins, they are usable as
general purpose input ports.
1-2) Clock
l DIRMCK
The master clock for such peripheral devices as DAC and ADC is output.
The operation mode of DIRMCK is selected according to the lock condition of PLL in the DIR block and
settings for the control register. The DIRMCK output modes are as follows.
- When PLL in the DIR block is not locked (/LOCK=H) ----- (1)
DIRMCK outputs 12.288MHz.
- When PLL in the DIR block is locked (/LOCK=L) and CKMOD=1 ----- (2)
DIRMCK outputs 12.288MHz
- When PLL in the DIR block is locked (/LOCK=L) and CKMOD=0
DIRMCK outputs according to the setting of LOCKMOD1-0.
LOCKMOD1
LOCKMOD0
Normal rate
Double rate
0
256fs
0
1
256fs
128fs
1
X
256fs
12.288MHz -(3)
The mode like the above (1), (2) and (3) in which the XI's divided clock of 12.288 MHz is output from
DIRMCK is referred to as "free-run mode".
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相关代理商/技术参数 |
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| YSS940 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:ADAMB Advanced Digital Audio Multi channel decode processor |
| YSS943 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:ADAMB Advanced Digital Audio Multi channel decode processor |
| YSS944 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:ADAMB Advanced Digital Audio Multi channel decode processor |
| YSS950 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:DAP1 Digital Audio Processor |
| YST 35-22 P24 C3 | 制造商:n/a 功能描述:Thyristor Puck |
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