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参数资料
| 型号： | YSS932 |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封装： | SQFP-128 |
| 文件页数： | 3/24页 |
| 文件大小： | 335K |
| 代理商： | YSS932 |
YSS932
11
l /LOCK, ERR, DIRINT
The same data as LOCKN, DIRERR, DIRINT of DIR STATUS Register are output from /LOCK, ERR/BS,
DIRINT pins respectively.
The DIRERR data is output from ERR/BS pin at BSMOD=0 setting.
l DBL
The information, whether the DDIN input signal is a double rate signal, is output from the DBL/V pin at
VMOD=0 setting.
If PLL in the DIR block is locked at double rate and the free-run mode is not used, “H” level is output.
If PLL in the DIR block is locked at normal rate or the free-run mode is used, “L” level is output.
1-5) Analog circuit for PLL in DIR block
l DIRPCO, DIRPRO
These are capacitor and resistor connection pins for PLL in DIR block. As shown below, connect a 4700pF
capacitor and an 8.2k
resistor between DIRPCO and AVSS as close as physically possible to DIRPCO and
a 5.1k
resistor between DIRPRO and AVSS as close as physically possible to DIRPRO.
DIRPCO
4700pF
5.1k
DIRPRO
AVSS
8.2k
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