参数资料
| 型号： | ZL2008ALAFT1 |
| 厂商： | Intersil |
| 文件页数： | 40/42页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 1,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 5.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ZL2008
Revision History (Continued)
Rev. #
Description
Date
FN6859.1 Added Note 15: “Nominal capacitance of logic pins is 5pF”. Added Note 15 callouts to Logic Output Low, V OL and Logic
Output High, V OH parameters.
Changed “Logic Input Bias Current” parameter to “Logic Input Leakage Current”. Changed Logic Input Leakage Current
October 2009
Min from -10μA to -250nA and Max from 10μA to 250nA.
Removed “MGN Input Bias Current” line from table.
Changed “Power Good V OUT Low Threshold” parameter to “Power Good V OUT Threshold” and removed “Power Good V OUT
High Threshold” line from table.
Page 10:
Removed 2 paragraphs as follows:
“The ZL2008 can be configured by simply connecting its pins according to the tables provided in the following sections…
I 2 C/SMBus interface using an available computer and the included USB cable.”
“Application notes and … local Zilker Labs sales office to order an evaluation kit”
Throughout: Changed all referenced Zilker App note numbers to newly assigned Intersil numbers (e.g. AN33 -> AN2033)
“Current Limit Threshold Selection” on page 21. In paragraph below Figure 16, changed “The current sensing method can
be selected via the I 2 C/SMBus interface.” to “The current sensing method can be selected using the CFG2 pin as shown
in Tables 26 and 28 or via the I 2 C/SMBus interface.” In 3 rd paragraph below Figure 16, changed “This is to avoid taking
a reading just after a current load step” to “This is to avoid taking a reading just after a switching transition”. Added “Note
that IOUT_CAL_GAIN is set to 2m Ω by default.” to end of last paragraph.
Replaced Table 25. Phase Offset Pin-strap Settings on page 30 (changed “CFG2 Pin” column to “R CFG2 ” and added
“Current Sense” column).
Table 26. Phase Offset Resistor Settings on page 30. Added “Current Sense” column and R CFG2 rows from 42.2k Ω through
162k Ω and corresponding Phase Offset rows.
On page 30: 2 nd column, 1 st paragraph, changed “The phase offset of (multi-phase) current sharing devices is
automatically set to a value between 0° and 337.5° in 22.5° increments as follows: Phase Offset = SMBus Address[4:0]
–Current Share Position * 22.5°” to “The phase offset of a current sharing group is automatically set to a value between
0° and 337.5° in 22.5° increments as follows: Phase Offset = (SMBus Address[4:0] –Current Share Position) * 22.5°”
Added “The phase of the individual members in a group are spread evenly from the phase offset of the group.”
Table 28. Current Share Position Settings on page 33. Added “Current Sense” column. Added R CFG2 rows from 42.2k Ω
through 82.5k Ω and corresponding Current Share Position rows.
Removed former Table 35. Snapshot Parameters
“Snapshot Parameter Capture” on page 35. Added “See AN2033 for details on using the Snapshot in addition to the
parameters supported.” to 2 nd paragraph
On page 4, corrected:
“Analog Input Voltages for ISENA Pin. . . . . . . . . . . . . . . . . . . . .1.5V to 30V”
to:
“Analog Input Voltages for ISENA Pin. . . . . . . . . . . . . . . . . . . .-1.5V to 6.5V”
On page 21, Table 14, added “DCR V LIM (mV)” column. Renamed “Threshold Voltage” column to “R DS V LIM ”
On page 22, Table 15, added “DCR V LIM (mV)” column. Renamed “V LIM ” column to “R DS V LIM ”
On page 21, in second column, first paragraph, changed “Note that IOUT_CAL_GAIN is set to 2m Ω by default.” to “By
default, the IOUT_CAL_GAIN is set to 1m Ω for DCR mode and 2m Ω for RDS mode.”
In Table 14 on page 21, removed “ (Voltage seen on 2m Ω )” from caption
In Table 15 on page 22, removed “(Voltage seen on 2m Ω )” from caption
“Power Good” on page 16, changed 2nd sentence from “...if the output is within -10%/+15% of the target voltage.” to “...if November 2009
the output is within -10% of the target voltage.”
Replaced last paragraph in “Power Good” section.
Change marketing part number to ZL2008ALBFT to note firmware revision.
40
FN6859.4
April 29, 2011
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| ZL2008ALBFT | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ZL2008ALBFT1 | 功能描述:IC REG CTRLR BUCK PWM VM 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ZL2008EVAL1Z | 功能描述:EVALUATION BOARD FOR ZL2008 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ZL20200 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Dual Band IS136/AMPS Transceiver |
| ZL20200_06 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Dual Band IS136/AMPS Transceiver |
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