参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 1/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
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Digital DC/DC Controller with Drivers and Auto
Compensation
ZL6105
The ZL6105 is a digital power controller with integrated
MOSFET drivers. Auto compensation eliminates the need for
manual compensation design work. Adaptive performance
optimization algorithms improve power conversion efficiency.
Zilker Labs Digital-DC? technology enables a blend of power
conversion performance and power management features.
The ZL6105 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 3.3V to a
multiphase current sharing supply operating from a 12V input.
The ZL6105 eliminates the need for complicated power supply
managers as well as numerous external discrete components.
The ZL6105 uses the I 2 C/SMBus? with PMBus? protocol for
communication with a host controller and the Digital-DC bus
for communication between Zilker Labs devices.
The ZL6105 is pin for pin compatible with the ZL2008. The
POLA V OUT table and compensation table have been removed.
A new single resistor V OUT table and the Auto Compensation
feature have been added.
Related Literature
? AN2032 , “NLR Configuration for DDC Products”
? AN2033 , “Zilker Labs PMBus Command Set - DDC Products”
? AN2034 , “Configuring Current Sharing on the ZL2004 and
ZL2006”
? AN2035 , “Compensation Using CompZL?”
Features
Power Conversion
? Efficient Synchronous Buck Controller
? Auto Compensating PID Filter
? Adaptive Light Load Efficiency Optimization
? 3V to 14V Input Range
? 0.54V to 5.5V Output Range (with margin)
? ±1% Output Voltage Accuracy
? Internal 3A MOSFET Drivers
? Fast Load Transient Response
? Current Sharing and Phase Interleaving
? Snapshot? Parameter Capture
? Pb-Free (RoHs Compliant)
Power Management
? Digital Soft-start/stop
? Power-Good/Enable
? Voltage Tracking, Sequencing and Margining
? Voltage, Current and Temperature Monitoring
? I 2 C/SMBus Interface, PMBus Compatible
? Output Voltage and Current Protection
? Internal Non-volatile Memory (NVM)
Applications
? Servers/Storage Equipment
? Telecom/Datacom Equipment
? Power Supply Modules
V
EN PG PH_EN FC ILIM CFG UVLO V25
VR VDD
100
95
90
V OUT = 3.3V
V OUT = 1.5V
SS
VTRK
MGN
SYNC
DDC
POWER
MANAGEMENT
LDO
DRIVER
BST
GH
SW
85
80
75
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
CURRENT
GL
VSEN+
VSEN-
ISENA
70
65
SCL
SDA
SALRT
I 2 C
MONITOR
ADC
SENSE
TEMP
SENSOR
ISENB
60
55
50
0
V IN = 12V
f SW = 400kHz
Circuit of Figure 4 3
2 4 6 8
10
12
14
16
18
20
SA
XTEMP
PGND SGND DGND
Load Current (A)
FIGURE 1. BLOCK DIAGRAM
FIGURE 2. EFFICIENCY vs LOAD CURRENT
December 19, 2013
FN6906.5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011-2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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