参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 14/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ZL6105
TABLE 5. ZL6105 START-UP SEQUENCE
STEP #
1
STEP NAME
Power Applied
DESCRIPTION
Input voltage is applied to the ZL6105’s VDD pin
TIME DURATION
Depends on input supply ramp
time
2
Internal Memory Check
The device will check for values stored in its internal memory. This step Approximately 5ms to 10ms
is also performed after a Restore command.
(device will ignore an enable
3
4
Multi-mode Pin Check
Device Ready
The device loads values configured by the multi-mode pins.
The device is ready to accept an enable signal.
signal or PMBus traffic during this
period)
?
5
Pre-ramp Delay
The device requires a minimum delay period following an enable signal ?
Soft-Start Delay and Ramp Times
It may be necessary to set a delay from when an enable signal is
received until the output voltage starts to ramp to its target
value. In addition, the designer may wish to precisely set the time
required for V OUT to ramp to its target value after the delay period
has expired. These features may be used as part of an overall
inrush current management strategy or to precisely control how
fast a load IC is turned on. The ZL6105 gives the system designer
several options for precisely and independently controlling both
the delay and ramp time periods.
The ZL6105 has a minimum TON_DELAY requirement that is a
function of the operating mode. Table 8 shows the different
mode configurations and the minimum TON_DELAY required for
each mode. Current sharing is configured with the
ISHARE_CONFIG PMBus command, Auto compensation is
configured with the AUTO_COMP_CONFIG command, and
Standby Mode is configured as Low Power with the
USER_CONFIG command. See Application Note AN2033 for
details.
TABLE 7. SS RESISTOR SETTINGS
The soft-start delay period begins when the EN pin is asserted
and ends when the delay time expires. The soft-start delay period
is set using the SS pin.
The soft-start ramp timer enables a precisely controlled ramp to
the nominal V OUT value that begins once the delay period has
expired. The ramp-up is guaranteed monotonic and its slope may
be precisely set using the SS pin.
The soft start delay and ramp times can be set to standard
values according to Table 6.
TABLE 6. SOFT-START PIN-STRAP SETTINGS
R SS
(k Ω)
13.3
14.7
16.2
17.8
19.6
21.5
23.7
DELAY TIME
(ms)
5
10
RAMP TIME
(ms)
2
5
10
20
2
5
10
SS PIN
LOW
DELAY TIME
(ms)
5
RAMP TIME
(ms)
2
26.1
28.7
20
2
OPEN
HIGH
5
10
5
10
31.6
34.8
15
5
10
38.3
20
If the desired soft-start delay and ramp times are not one of the values
listed in Table 6, the times can be set to a custom value by connecting a
42.2
2
resistor from the SS pin to SGND using the appropriate resistor value
from Table 7. The value of this resistor is measured upon start-up or
Restore and will not change if the resistor is varied after power has been
applied to the ZL6105.
The soft-start delay and ramp times can also be set to custom
values via the I 2 C/SMBus interface. When the SS delay time is
set to 0ms, the device will begin its ramp-up after the internal
circuitry has initialized (approximately 2ms). When the soft-start
ramp period is set to 0ms, the output will ramp up as quickly as
46.4
51.1
56.2
61.9
68.1
75
82.5
20
30
5
10
20
2
5
10
20
the output load capacitance and loop settings will allow. It is
generally recommended to set the soft-start ramp to a value
greater than 500μs to prevent inadvertent fault conditions due to
excessive in-rush current.
14
FN6906.5
December 19, 2013
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