参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 8/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
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ZL6105
Electrical Specifications V DD = 12V, T A = -40°C to +85°C unless otherwise noted. Typical values are at T A = +25°C. Boldface limits apply over
the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Current Sense Input Bias Current
(V out Referenced, V out < 4.0V)
Soft-start Delay Duration Range
Soft-start Delay Duration Accuracy
Soft-start Ramp Duration Range
CONDITIONS
ISENA
ISENB
Set using SS pin or resistor (Note 15)
Set using I 2 C/SMBus (Note 15)
Turn-on delay (Note 15)
Turn-off delay (Note 15)
Set using SS pin or resistor
(Note 19)
-1
-100
5
0.005
-
-
2
TYP
–
–
–
–
-0.25/+4
-0.25/+4
–
(Note 19)
1
100
30
500
-
-
20
UNIT
μA
μA
ms
s
ms
ms
ms
Soft-start Ramp Duration Accuracy
Set using I 2 C
0
–
–
100
200
–
ms
μs
Logic Input/Output Characteristics
Logic Input Leakage Current
Logic Input Low, V IL
Logic Input OPEN (N/C)
Logic Input High, V IH
Logic Output Low, V OL
Logic Output High, V OH
EN, SCL, SDA pins
Multi-mode logic pins
I OL ≤ 4mA (Note 20)
I OH ≥ -2mA (Note 20)
-250
–
–
2.0
–
2.25
–
–
1.4
–
–
–
250
0.8
–
–
0.4
–
nA
V
V
V
V
V
Oscillator and Switching Characteristics
Switching Frequency Range
200
–
1400
kHz
Switching Frequency Set-point Accuracy
Maximum Pwm Duty Cycle
Minimum Sync Pulse Width
Input Clock Frequency Drift Tolerance
Predefined settings (See Table 11)
Factory default
External clock source
-5
95
150
-13
–
–
–
–
5
–
–
13
%
%
ns
%
Gate Drivers
High-side driver voltage (V BST -V SW )
–
4.5
–
V
High-side Driver Peak Gate Drive
Current (Pull-down)
High-side Driver Pull-up Resistance
High-side Driver Pull-down Resistance
Low-side Driver Peak Gate
Drive Current (Pull-up)
Low-side Driver Peak Gate
Drive Current (Pull-down)
Low-side Driver Pull-up Resistance
Low-side Driver Pull-down Resistance
(V BST -V SW ) = 4.5V
(V BST -V SW ) = 4.5V, (V BST -V GH ) = 50mV
(V BST -V SW ) = 4.5V, (V GH -V SW ) = 50mV
V R = 5V
V R = 5V
V R = 5V, (V R -V GL ) = 50mV
V R = 5V, (V GL -PGND) = 50mV
2
–
–
–
–
–
–
3
0.8
0.5
2.5
1.8
1.2
0.5
–
2
2
–
–
2
2
A
Ω
Ω
A
A
Ω
Ω
Switching Timing
Gh Rise and Fall Time
Gl Rise and Fall Time
(V BST -V SW ) = 4.5V, C LOAD = 2.2nF
V R = 5V, C LOAD = 2.2nF
–
–
5
5
20
20
ns
ns
Tracking
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy
VTRK Regulation Accuracy
VTRK = 5.5V
100% Tracking, V OUT -VTRK, no prebias
100% Tracking, V OUT -VTRK
–
-100
-1
110
–
–
200
+ 100
1
μA
mV
%
Fault Protection Characteristics
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
Configurable via I 2 C/SMBus
Factory default
2.85
-150
–
–
–
3
16
150
–
V
mV
%
Configurable via
I 2 C/SMBus
0
–
100
%
8
FN6906.5
December 19, 2013
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