参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 16/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ZL6105
Logic
high
SYNC
SYNC
200 kHz – 1.33MHz
N/ C
ZL
A) SYNC = output
Logic
200kHz – 1.4MHz
N/ C
ZL
B) SYNC = input
N/C
high
SYNC
Open
SYNC
SYNC
200kHz – 1.4MHz
ZL
OR
Logic
ZL
OR
R SYNC
ZL
low
C) SYNC = Auto Detect
FIGURE 10. SYNC PIN CONFIGURATIONS
TABLE 11. SWITCHING FREQUENCY RESISTOR SETTINGS
Power Train Component Selection
R SYNC
(k Ω )
10
11
12.1
13.3
14.7
16.2
17.8
f SW
(kHz)
200
222
242
267
296
320
364
R SYNC
(k Ω )
26.1
28.7
31.6
34.8
38.3
46.4
51.1
f SW
(kHz)
533
571
615
727
800
889
1000
The ZL6105 is a synchronous buck converter that uses external
MOSFETs, inductor and capacitors to perform the power
conversion process. The proper selection of the external
components is critical for optimized performance.
To select the appropriate external components for the desired
performance goals, the power supply requirements listed in
Table 12 must be known.
TABLE 12. POWER SUPPLY REQUIREMENTS
EXAMPLE
19.6
21.5
23.7
400
421
471
56.2
68.1
1143
1333
PARAMETER
Input Voltage (V IN )
Output Voltage (V OUT )
RANGE
3V to 14V
0.6V to 5.0V
VALUE
12V
1.2V
Output Current (I OUT )
0A to ~25A
20A
The switching frequency can also be set to any value between
200kHz and 1.33MHz using the I 2 C/SMBus interface. The available
frequencies below 1.4MHz are defined by f SW = 8MHz/N, where the
whole number N is 6 ≤ N ≤ 40. See Application Note AN2033 for
details.
If a value other than f SW = 8MHz/N is entered using a PMBus
command, the internal circuitry will select the valid switching
frequency value that is closest to the entered value. For example,
if 810kHz is entered, the device will select 800kHz (N = 10).
Output Voltage Ripple
(V ORIP )
Output Load Step (I OSTEP )
Output Load Step Rate
Output Deviation Due to Load Step
Maximum PCB Temp.
Desired Efficiency
Other Considerations
<3% of V OUT
<I O
-
-
+120°C
-
Various
1% of V OUT
50% of I O
10A/μs
±50mV
+85°C
85%
Optimize for
When multiple Zilker Labs devices are used together, connecting
the SYNC pins together will force all devices to synchronize with
each other. The CFG1 pin of one device must set its SYNC pin as
an output and the remaining devices must have their SYNC pins
set as Auto Detect.
Note: The switching frequency read back using the appropriate
PMBus command will differ slightly from the selected values in
Table 11. The difference is due to hardware quantization.
16
small size
DESIGN GOAL TRADE-OFFS
The design of the buck power stage requires several
compromises among size, efficiency, and cost. The inductor core
loss increases with frequency, so there is a trade-off between a
small output filter made possible by a higher switching frequency
and getting better power supply efficiency. Size can be decreased
FN6906.5
December 19, 2013
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