参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 9/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
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ZL6105
Electrical Specifications V DD = 12V, T A = -40°C to +85°C unless otherwise noted. Typical values are at T A = +25°C. Boldface limits apply over
the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
UVLO Delay
Power Good V OUT Threshold
Power Good V OUT Hysteresis
Power Good Delay
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
CONDITIONS
Factory default
Factory default
Using pin-strap or resistor (Note 16)
Configurable via I 2 C/SMBus
Factory default
Configurable via I 2 C/SMBus
Factory default
(Note 19)
–
–
–
0
0
–
0
–
TYP
2.5
90
5
–
–
85
–
115
(Note 19)
-
–
–
200
500
–
110
–
UNIT
μs
% V OUT
%
ms
s
% V OUT
% V OUT
% V OUT
VSEN Undervoltage Hysteresis
Configurable via
I 2 C/SMBus
0
–
–
5
115
–
% V OUT
% V OUT
VSEN Undervoltage/Overvoltage
Fault Response Time
Current Limit Set-point Accuracy
Factory default
Configurable via I 2 C/SMBus
–
5
–
16
–
±10
–
60
–
μs
μs
% FS
(V OUT Referenced)
(Note 17)
Current Limit Set-point Accuracy
–
±10
–
% FS
(Ground Referenced)
(Note 17)
Current Limit Protection Delay
Temperature Compensation of
Current Limit Protection Threshold
Thermal Protection Threshold
(Junction Temperature)
Thermal Protection Hysteresis
Factory default
Configurable via I 2 C/SMBus
Factory default
I 2 C/SMBus
Configurable via
Factory default
Configurable via I 2 C/SMBus
–
1
100
–
-40
–
10
–
4400
125
–
15
–
32
12700
–
125
–
t SW
(Note 18)
t SW
(Note 18)
ppm/°C
°C
°C
°C
NOTES:
12. Does not include margin limits.
13. Percentage of Full Scale (FS) with temperature compensation applied.
14. V OUT measured at the termination of the VSEN+ and VSEN-sense points.
15. The device requires a minimum delay period following an enable signal and prior to ramping its output as described in “Soft-Start Delay and Ramp
16. Factory default Power Good delay is set to the same value as the soft-start ramp time. Refer to “Soft-Start Delay and Ramp Times” on page 14 for
further restrictions on PG Delay.
17. Percentage of Full Scale (FS) with temperature compensation applied
18. t SW = 1/f SW , where f SW is the switching frequency.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
20. Nominal capacitance of logic pins is 5pF.
9
FN6906.5
December 19, 2013
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