参数资料
| 型号： | ZL6105ALAFTR5546 |
| 厂商： | Intersil |
| 文件页数： | 6/35页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 36-QFN |
| 标准包装： | 100 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 1.4MHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 14 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页
ZL6105
Pin Descriptions (Continued)
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
LABEL
ISENA
VR
GL
PGND
SW
GH
BST
VDD (Note 3)
V25
XTEMP
DDC
MGN
CFG1
EN
PH_EN
TYPE (Note 1)
I
PWR
O
PWR
PWR
O
PWR
PWR
PWR
I
I/O
I
I, M
I
I
DESCRIPTION
Differential voltage input for current limit. High voltage tolerant.
Internal 5V reference used to power internal drivers.
Low side FET gate drive.
Power ground. Connect to low impedance ground plane.
Drive train switch node.
High-side FET gate drive.
High-side drive boost voltage.
Supply voltage.
Internal 2.5V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 diode connected transistor.
Digital-DC Bus. (Open Drain) Interoperability between Zilker Labs devices.
Signal that enables margining of output voltage.
Configuration pin. Used to setup clock synchronization and sequencing.
Enable input (active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.
Phase enable input (active high). Pull-up to enable phase and pull-down to disable phase for current
sharing.
35
36
ePad
CFG2
PG
SGND
I, M
O
PWR
Configuration pin. Sets the phase offset (single-phase) or current sharing group position (multi-phase).
Power-good output.
Exposed thermal pad. Common return for analog signals; internal connection to SGND. Connect to low
impedance ground plane.
NOTES:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pin dependents. (Refer to “Multi-mode Pins” on page 11).
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. V DD is measured internally and the value is used to modify the PWM loop gain.
Ordering Information
PART NUMBER
(Notes 5, 6)
ZL6105ALAF
ZL6105ALAFT (Note 4)
ZL6105ALAFTK (Note 4)
6105
6105
6105
PART
MARKING
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(Pb-free)
36 Ld QFN
36 Ld QFN
36 Ld QFN
PKG.
DWG. #
L36.6x6C
L36.6x6C
L36.6x6C
NOTES:
4. Please refer to TB347 for details on reel specifications.
5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
6. For Moisture Sensitivity Level (MSL), please see device information page for ZL6105 . For more information on MSL please see techbrief TB363 .
6
FN6906.5
December 19, 2013
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