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参数资料
| 型号： | ZXLB1600X10TC |
| 厂商： | Diodes Inc |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC REG BST FLYBK ADJ 10MA 10MSOP |
| 标准包装： | 4,000 |
| 类型： | 升压，反激式 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.6 V ~ 28 V |
| 输入电压： | 1.6 V ~ 5.5 V |
| 频率 - 开关： | 最高 500kHz |
| 电流 - 输出： | 10mA |
| 同步整流器： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP |
LAST TIME BUY
ZXLB1600
APPLICATION NOTES
in this way. However, some non-linearity in the above
Adjusting output voltage
When connected as shown in the typical application
circuit, the ZXLB1600 will produce a nominal output
voltage of 28V. This can be adjusted by one of the three
methods described below.
1) Output voltage adjustment by external resistors
The internal reference and resistor divider network R1
and R2 set a nominal output of 28V. However, this
network is accessible at the FB pin and can be shunted
by means of external resistors to set different nominal
output voltages. The potential divider defines output
voltage according to the relationship:
V OUT(dc) = (R1+R2)/R1 x 1.23V
When using external resistors, these should be chosen
with lower values than the internal resistors to
minimize errors caused by the ±25% absolute value
variation of the internal resistors. The internal resistors
have high values in order to minimize these errors.
The following table gives suggested E24/E96 resistor
values for various output voltages.
expression may occur at values of VADJ below
approximately 0.5V.
Also note that when driving the ADJ pin, the control
voltage must have sufficiently low impedance to sink
the bias current of the internal reference.(10 A max).
3) PWM output adjustment
A Pulse Width Modulated (PWM) signal can be applied
to the EN pin in order to adjust the output voltage to a
value below the value set in in 1) or 2). This method of
adjustment permits the device to be turned on and the
output voltage set by a single logic signal applied to the
EN pin. No external resistors or capacitors are required
and the amplitude of the control signal is not critical,
providing it conforms to the limits defined in the
electrical characteristics.
Two modes of adjustment are possible as described
below:
Filtered 'DC' mode
If a PWM signal of 10kHz or higher is applied to the EN
pin, the device will remain active when the EN pin is
low. However, the input to the internal low pass filter
Required
output
voltage
5V
12V
18V
20V
22V
25V
External resistor
across R2
280k
715k
1M
1.15 M
1.15M
1.2 M
External resistor
across R1
91k
82k
75k
75k
68.1k
62k
will be switched alternately from V REF to ground, with a
duty cycle (D) corresponding to that of the PWM signal.
This will present a filtered dc voltage equal to the duty
cycle multiplied by V REF to the control loop and will
produce a dc output voltage lower than the maximum
set value. This voltage is given by:
V OUT = 28 x D
A square wave signal applied to the EN pin, for
example, will turn the device on and produce a nominal
regulated output of 14V.
2) Output adjustment by external voltage
The internal voltage reference (Pin ADJ) may be
overdriven by an external control voltage to set the
output voltage. The relationship between applied
voltage (V ADJ ) and output voltage (V OUT ) is:
V OUT = 22.86 x V ADJ
Note that the output can be set to any value between
the input voltage and the maximum operating voltage
ISSUE 3 - SEPTEMBER 2003
11
SEMICONDUCTORS
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