参数资料
型号: ZXLB1600X10TC
厂商: Diodes Inc
文件页数: 6/16页
文件大小: 0K
描述: IC REG BST FLYBK ADJ 10MA 10MSOP
标准包装: 4,000
类型: 升压,反激式
输出类型: 可调式
输出数: 1
输出电压: 1.6 V ~ 28 V
输入电压: 1.6 V ~ 5.5 V
频率 - 开关: 最高 500kHz
电流 - 输出: 10mA
同步整流器:
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
LAST TIME BUY
ZXLB1600
Filtered PWM operation
The input of an internal low pass filter is switched to
V REF when the EN pin is high and switched to ground
when the EN pin is low. The output of this filter drives
the comparator within the control loop. A continuous
high state on EN therefore provides a filtered voltage of
value Vref to the comparator and the control loop
regulates the output to a nominal value of 28V.
However, by varying the duty cycle (D) of the EN signal
at a suitably high frequency (f>10kHz), the control loop
will see a voltage, that has an average value equal to
the duty cycle multiplied by V REF . This provides a
means of adjusting the output voltage to a lower value.
It also allows the device to be both turned on and
adjusted with a single signal at the 'EN' pin. The output
during this mode of operation will be a dc voltage equal
Low battery detection
A comparator driving an open drain NMOS output
transistor performs the low battery flag function. The
detection threshold (battery voltage falling) is set to
1.98V nominal with internal resistors R3 and R4, but
this can be changed by shunting the internal potential
divider with two external resistors at pin 'LBT'.
Operation is such that the output transistor will be
turned on when the battery voltage falls below the
detection threshold.
V BLT = 1.21 x (R3+R4)/R4
A small amount (nominal 20mV) of hysteresis is
provided to aid clean switching. The low battery
detection circuit remains active when 'EN' is low.
to D x 28V
Gated PWM operation
The internal circuitry of the ZXLB1600 is turned off
when no signal is present on the 'EN' pin for more than
120 s (nominal). A low frequency signal applied to the
EN pin will therefore gate the device 'on' and 'off' at the
gating frequency and the duty cycle of this signal can
be varied to provide a 'chopped' output voltage equal
to D x 28V. For best accuracy, the gating frequency
should be made as low as possible (e.g. below 1kHz),
such that the turn off delay of the chip is only a small
proportion of the gating period.
Further details of setting output current are given in the
application notes.
ISSUE 3 - SEPTEMBER 2003
SEMICONDUCTORS
6
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