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参数资料
| 型号： | 3336-01 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 8/13页 |
| 文件大小： | 0K |
| 描述： | EVAL KIT FOR PE3336 |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 类型： | 整数 N/PLL |
| 频率： | 3GHz |
| 适用于相关产品： | PE3336 |
| 已供物品： | 板，线缆，软件 |
| 其它名称： | 3336-1 3336-1-ND PE3336 PE3336 EK |
Product Specification
PE3336
Page 4 of 13
2005-2011 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0033-05
│ UltraCMOS RFIC Solutions
23
Fin
ALL
Input
Prescaler complementary input. A bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50
resistor
directly to the ground plane.
24
GND
ALL
Ground.
25
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding VDD
pin 31.
26
VDD-fp
ALL
(Note 1)
VDD for fp. Can be left floating or connected to GND to disable the fp output.
27
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on
Dout through enhancement register programming.
28
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
29
Cext
ALL
Output
Logical “NAND” of PD_
U and PD_D terminated through an on chip, 2 k
series resistor. Connecting Cext to an external capacitor will low pass filter
the input to the inverting amplifier used for driving LD.
30
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
32
PD_
D
ALL
Output
PD_
D is pulse down when f
p leads fc.
33
PD_
U
ALL
PD_
U is pulse down when f
c leads fp.
35
VDD-fc
ALL
(Note 1)
VDD for fc can be left floating or connected to GND to disable the fc output.
36
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled
through enhancement register programming or by floating or grounding VDD
pin 38.
31,37
GND
ALL
Ground.
38,39
GND
ALL
Ground.
40
fr
ALL
Input
Reference frequency input.
41
LD
ALL
Output
Lock detect and open drain logical inversion of CEXT. When the loop is in
lock, LD is high impedance, otherwise LD is a logic low (“0”).
42
Enh
Serial, Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits
are functional.
43
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
44
R0
Direct
Input
R Counter bit0 (LSB).
45
R1
Direct
Input
R Counter bit1.
46
R2
Direct
Input
R Counter bit2.
47
R3
Direct
Input
R Counter bit3.
48
GND
ALL
(Note 1)
Ground.
34
NC
ALL
No connection.
Table 1. Pin Descriptions (continued)
Notes: 1. All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc outputs.
2. All digital input pins have 70 k
pull-down resistors to ground.
Pin No.
Pin Name
Interface Mode
Type
Description
Obsolete
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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